From f36fdf940dcc7c6600238b23a2317bcdf3e30b1e Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 4 May 2022 21:18:24 +0000 Subject: [PATCH] removed instruction misaligned tests from trap tests, signatures --- .../references/WALLY-trap-01.reference_output | 10 ++-------- .../references/WALLY-trap-s-01.reference_output | 10 ++-------- .../references/WALLY-trap-u-01.reference_output | 10 ++-------- .../rv32i_m/privilege/src/WALLY-trap-01.S | 3 +-- .../rv32i_m/privilege/src/WALLY-trap-s-01.S | 3 +-- .../rv32i_m/privilege/src/WALLY-trap-u-01.S | 3 +-- .../references/WALLY-trap-01.reference_output | 16 ++-------------- .../references/WALLY-trap-s-01.reference_output | 16 ++-------------- .../references/WALLY-trap-u-01.reference_output | 16 ++-------------- .../rv64i_m/privilege/src/WALLY-trap-01.S | 3 +-- .../rv64i_m/privilege/src/WALLY-trap-s-01.S | 3 +-- .../rv64i_m/privilege/src/WALLY-trap-u-01.S | 3 +-- 12 files changed, 18 insertions(+), 78 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output index 33a069d6d..a6719be99 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output @@ -1,7 +1,4 @@ -00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts -00000000 # mcause from instruction addr misaligned fault -8000013a # mtval of faulting instruction adress -00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # mcause from an instruction access fault 00000000 # mtval of faulting instruction address (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 @@ -57,10 +54,7 @@ 00000000 # mtval for mext interrupt (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) -00000222 # mideleg after attempted write of all 1's (only some bits are writeable) -00000000 # mcause from instruction addr misaligned fault -8000013a # mtval of faulting instruction adress -00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000222 # mideleg after attempted write of all 1's (only some bits are writeable) # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # mcause from an instruction access fault 00000000 # mtval of faulting instruction address (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index 724d4e5e8..e67e60703 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -1,10 +1,7 @@ 00000aaa # readback value from writing mie to enable interrupts 0000000b # Test 5.3.1.4: mcause from ecall going from M mode to S mode 00000000 # mtval of ecall (*** defined to be zero for now) -00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 # scause from instruction addr misaligned fault -8000013a # stval of faulting instruction adress -00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # scause from an instruction access fault 00000000 # stval of faulting instruction address (0x0) 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 @@ -59,10 +56,7 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 0000000b # scause from M mode ecall 00000000 # stval of ecall (*** defined to be zero for now) -00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 # scause from instruction addr misaligned fault -8000013a # stval of faulting instruction adress -00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # scause from an instruction access fault 00000000 # stval of faulting instruction address (0x0) 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output index 7670852ea..e96905213 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -1,10 +1,7 @@ 00000aaa # readback value from writing mie to enable interrupts 0000000b # Test 5.3.1.4: mcause from ecall going from M mode to U mode 00000000 # mtval of ecall (*** defined to be zero for now) -00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 # scause from instruction addr misaligned fault -8000013a # stval of faulting instruction adress -00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # scause from an instruction access fault 00000000 # stval of faulting instruction address (0x0) 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 @@ -52,10 +49,7 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 0000000b # scause from M mode ecall 00000000 # stval of ecall (*** defined to be zero for now) -00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 # scause from instruction addr misaligned fault -8000013a # stval of faulting instruction adress -00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # scause from an instruction access fault 00000000 # stval of faulting instruction address (0x0) 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S index 35fea2b98..4700309b1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S @@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented // test 5.3.1.4 Basic trap tests -jal cause_instr_addr_misaligned +// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled. jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt @@ -61,7 +61,6 @@ jal cause_m_ext_interrupt WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF -jal cause_instr_addr_misaligned jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S index 0c4477619..3218e1efb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S @@ -40,7 +40,7 @@ WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enabl GOTO_S_MODE -jal cause_instr_addr_misaligned +// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled. jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt @@ -73,7 +73,6 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF GOTO_S_MODE // Since we're running in M mode, this ecall will NOT be delegated to S mode -jal cause_instr_addr_misaligned jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S index 326f53625..5d4180a7a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S @@ -40,7 +40,7 @@ WRITE_READ_CSR mie, 0xFFFF GOTO_U_MODE -jal cause_instr_addr_misaligned +// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled. jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt @@ -70,7 +70,6 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF GOTO_U_MODE -jal cause_instr_addr_misaligned jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index d8f7f8b40..d1cf44230 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -1,11 +1,5 @@ 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts -00000000 -00000000 # mcause from instruction addr misaligned fault -00000000 -800003d2 # mtval of faulting instruction adress (0x800003d3) -00000000 -00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -00000000 +00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # mcause from an instruction access fault 00000000 00000000 # mtval of faulting instruction address (0x0) @@ -117,13 +111,7 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) ffffffff 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) -00000000 -00000000 # mcause from instruction addr misaligned fault -00000000 -800003d2 # mtval of faulting instruction adress (0x800003d3) -00000000 -00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -00000000 +00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # mcause from an instruction access fault 00000000 00000000 # mtval of faulting instruction address (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index 84519e037..fa362810f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -5,13 +5,7 @@ 00000000 # mtval of ecall (*** defined to be zero for now) 00000000 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 -00000000 # scause from instruction addr misaligned fault -00000000 -800003d2 # stval of faulting instruction adress (0x800003d3) -00000000 -00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 +00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # scause from an instruction access fault 00000000 00000000 # stval of faulting instruction address (0x0) @@ -121,13 +115,7 @@ ffffffff 00000000 # stval of ecall (*** defined to be zero for now) 00000000 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 -00000000 # scause from instruction addr misaligned fault -00000000 -800003d2 # stval of faulting instruction adress (0x800003d3) -00000000 -00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 -00000000 +00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # scause from an instruction access fault 00000000 00000000 # stval of faulting instruction address (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output index 7a1b3dcd8..d1a0c9019 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -5,13 +5,7 @@ 00000000 # mtval of ecall (*** defined to be zero for now) 00000000 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 -00000000 # scause from instruction addr misaligned fault -00000000 -800003d2 # stval of faulting instruction adress (0x800003d3) -00000000 -00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 +00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # scause from an instruction access fault 00000000 00000000 # stval of faulting instruction address (0x0) @@ -107,13 +101,7 @@ ffffffff 00000000 # stval of ecall (*** defined to be zero for now) 00000000 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 -00000000 # scause from instruction addr misaligned fault -00000000 -800003d2 # stval of faulting instruction adress (0x800003d3) -00000000 -00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 -00000000 +00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # scause from an instruction access fault 00000000 00000000 # stval of faulting instruction address (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S index 22928eb54..850086014 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S @@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // test 5.3.1.4 Basic trap tests -jal cause_instr_addr_misaligned +// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled. jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt @@ -61,7 +61,6 @@ jal cause_m_ext_interrupt WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF -jal cause_instr_addr_misaligned jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S index 8e72a6f1b..f9bf126eb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S @@ -40,7 +40,7 @@ WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enabl GOTO_S_MODE -jal cause_instr_addr_misaligned +// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled. jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt @@ -73,7 +73,6 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF GOTO_S_MODE // Since we're running in M mode, this ecall will NOT be delegated to S mode -jal cause_instr_addr_misaligned jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S index 104e03f36..f68e6cdd6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S @@ -40,7 +40,7 @@ WRITE_READ_CSR mie, 0xFFFF GOTO_U_MODE -jal cause_instr_addr_misaligned +// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled. jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt @@ -70,7 +70,6 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF GOTO_U_MODE -jal cause_instr_addr_misaligned jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt