Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh

@@ -3,7 +3,7 @@
 source  genSettings.sh
 tcpPort=1236
 
-instrs=10000000
+instrs=480000000
 checkOutDir="$outDir/checkpoint$instrs"
 checkIntermedDir="$checkOutDir/intermediate-outputs"
 
@@ -32,7 +32,7 @@ then
     # Post-Process GDB outputs
     ./parseState.py "$checkOutDir"
     ./fix_mem.py "$checkIntermedDir/ramGDB.txt" "$checkOutDir/ram.txt"
-    tail -n+$instrs "$outDir/$traceFile" > "$checkOutDir/$traceFile"
+    tail -n+$($instrs+1) "$outDir/$traceFile" > "$checkOutDir/$traceFile"
 else
     echo "You can change the number of instructions by editing the \"instrs\" variable in this script."
     echo "Have a nice day!"

wally-pipelined/src/cache/cachereplacementpolicy.sv

@@ -59,7 +59,7 @@ module cachereplacementpolicy
 	ReplacementBits[index] <= '0;
     end else begin
       RAdrD <= RAdr;
-      MemPAdrMD <= MemPAdrMD;
+      MemPAdrMD <= MemPAdrM;
       LRUWriteEnD <= LRUWriteEn;
       NewReplacementD <= NewReplacement;
       if (LRUWriteEnD) begin
@@ -84,6 +84,38 @@ module cachereplacementpolicy
       
     end else if (NUMWAYS == 4) begin : FourWay
 
+
+      // VictimWay is a function only of the current value of the LRU.
+      // binary encoding
+      //assign VictimWay[0] = BlockReplacementBits[2] ? BlockReplacementBits[1] : BlockReplacementBits[0];
+      //assign VictimWay[1] = BlockReplacementBits[2];
+
+      // 1 hot encoding
+      //| WayHit | LRU 2 | LRU 1 | LRU 0 |
+      //|--------+-------+-------+-------|
+      //|   0000 |     - | -     | -     |
+      //|   0001 |     1 | -     | 1     |
+      //|   0010 |     1 | -     | 0     |
+      //|   0100 |     0 | 1     | -     |
+      //|   1000 |     0 | 0     | -     |
+
+      assign VictimWay[0] = ~BlockReplacementBits[2] & ~BlockReplacementBits[0];
+      assign VictimWay[1] = ~BlockReplacementBits[2] & BlockReplacementBits[0];
+      assign VictimWay[2] = BlockReplacementBits[2] & ~BlockReplacementBits[1];
+      assign VictimWay[3] = BlockReplacementBits[2] & BlockReplacementBits[1];      
+
+      // New LRU bits which are updated is function only of the WayHit.
+      // However the not updated bits come from the old LRU.
+      assign LRUEn[2] = |WayHit;
+      assign LRUEn[1] = WayHit[3] | WayHit[2];
+      assign LRUEn[0] = WayHit[1] | WayHit[0];
+
+      assign LRUMask[2] = WayHit[1] | WayHit[0];
+      assign LRUMask[1] = WayHit[2];
+      assign LRUMask[0] = WayHit[0];
+      
+/* -----\/----- EXCLUDED -----\/-----
+
       // selects
       assign LRUEn[2] = 1'b1;
       assign LRUEn[1] = WayHit[3];      
@@ -93,16 +125,19 @@ module cachereplacementpolicy
       assign LRUMask[0] = WayHit[1];
       assign LRUMask[1] = WayHit[3];      
       assign LRUMask[2] = WayHit[3] | WayHit[2];
+ -----/\----- EXCLUDED -----/\----- */
 
       for(index = 0; index < NUMWAYS-1; index++)
 	assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : BlockReplacementBits[index];
 
+/* -----\/----- EXCLUDED -----\/-----
       assign EncVicWay[1] = BlockReplacementBits[2];
       assign EncVicWay[0] = BlockReplacementBits[2] ? BlockReplacementBits[0] : BlockReplacementBits[1];
 
       onehotdecoder #(2) 
       waydec(.bin(EncVicWay),
 	     .decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3]}));
+ -----/\----- EXCLUDED -----/\----- */
 
     end else if (NUMWAYS == 8) begin : EightWay
 

wally-pipelined/src/cache/dcache.sv

@@ -142,6 +142,8 @@ module dcache
 
   logic LRUWriteEn;
   
+  logic [NUMWAYS-1:0] VDWriteEnableWay;
+
   // Read Path CPU (IEU) side
 
   mux4 #(INDEXLEN)
@@ -167,7 +169,7 @@ module dcache
 		      .WAdr,
 		      .PAdr(MemPAdrM),
 		      .WriteEnable(SRAMWayWriteEnable),
-		      .VDWriteEnable,		      
+		      .VDWriteEnable(VDWriteEnableWay),
 		      .WriteWordEnable(SRAMWordEnable),
 		      .TagWriteEnable(SRAMBlockWayWriteEnableM), 
 		      .WriteData(SRAMWriteData),
@@ -329,6 +331,8 @@ module dcache
 	      .d(NextFlushWay),
 	      .q(FlushWay));
 
+  assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}};  
+
   assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
 
   assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];

wally-pipelined/src/ifu/CodeAligner.py

@@ -0,0 +1,98 @@
+import os
+
+# Kevin Wan kewan@hmc.edu 10/27/2021
+def read_input(filename):  #1
+    """Takes in a string filename and outputs the parsed verilog code by line into a list
+    such that each element of the list is one line of verilog code as a string."""
+    lineOfCode = []
+    input_file = open(filename, 'r')
+    for line in input_file:
+        lineOfCode.append(line)
+    return lineOfCode
+###################################################################################
+def ID_start(GiantString):#2
+    """takes in the list of sv file lines, outputs the location that variable names should start"""
+    VarLoc = 0 
+    VarLineNum = None
+    for lines in GiantString:
+        if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds. 
+            if "[" in lines and "]" in lines:# need to account for these space
+                NowLoc = lines.find(']') + 3# column number in sv code when 1st char of the var name should appear. 
+                if NowLoc>VarLoc: 
+                    VarLoc = NowLoc
+                    VarLineNum = GiantString.index(lines) # Update this number if new record is made. 
+            else:   
+                NowLoc = lines.find('logic') + 7 # same as before.
+                if NowLoc>VarLoc: 
+                    VarLoc = NowLoc
+                    VarLineNum = GiantString.index(lines)
+    #print("Furthest variable appears on line", VarLineNum + 1,VarLoc)   # Disable this line after debugging. 
+    return VarLoc
+##################################################################################
+def modified_logNew(GS,SOV): #3
+    Ind = SOV - 1 # SOV is for human readability, Ind is the character's index in computer, since computers count from 0's we need to correct it. 
+    Out = []
+    for l in GS:
+        lines = l.replace('\t',' ')
+
+        if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds. 
+            if "[" in lines and "]" in lines: # the line is an extended declaration. 
+                EditLoc = lines.find("]") # Re-finds the string index number of ]. 
+                VarLoc = FindCharRel(lines[EditLoc+1::]) + EditLoc + 1  # Checks where variable declaration currently is at. 
+                #print(VarLoc,lines[VarLoc])# VERIFIED
+                NewLine = Mod_Space_at(lines,VarLoc,VarLoc-Ind) 
+                Out.append(NewLine)# Verified0957 10272021
+            else:
+                EditLoc1 = lines.find('c') # Hopefully sees the c in 'logic'
+
+                VarLoc1 = FindCharRel(lines[EditLoc1+1::]) + EditLoc1 + 1
+                NewLine1 = Mod_Space_at(lines,VarLoc1,VarLoc1-Ind)
+
+                Out.append(NewLine1)# Verified 1005 10272021
+        else:
+            Out.append(lines)
+    return Out   
+################################################################################
+def write_to_output(filename,GiantString,OW=True,Lines_editted=None):   #4
+ """Filename is preferrably passed from the early function calls"""
+ """GiantString has all the corrected features in the code, each line is a good verilog code line"""
+ newname = filename
+ if not OW or OW =='f':   #which means no overwrite (create a new file)
+  Decomposed=filename.split('.')
+  newname = Decomposed[0] + "_AL." + Decomposed[1] # AL for aligned. 
+  
+ OutFile = open(newname,'w') # This step should create a new file. 
+ OutFile.writelines(GiantString)
+ OutFile.close()
+ print("Success! " + newname + " Now contains an aligned file!")
+ return newname
+#################################################################################
+
+def FindCharRel(Ln):
+    #returns the computer location of a character's first occurence
+    for num in range(len(Ln)):
+        if Ln[num] != " ":
+            return num 
+
+
+def Mod_Space_at(Ln,loc,diff):
+    #loc is the varLoc from mln, diff is varLoc - Ind
+    if diff > 0: # to delete
+        NewString = Ln[:(loc-diff)] + Ln[loc:]
+        
+    if diff < 0: # to add
+        NewString = Ln[:loc] + (-diff)*" " + Ln[loc:]
+    if diff == 0:
+        NewString = Ln
+    
+    return NewString
+
+def main_filehandler(overwrite=False):
+    for filename in os.listdir():
+        if ".py" not in filename:
+            GiantString = read_input(filename)
+            SOV = ID_start(GiantString)
+            ModifiedGS = modified_logNew(GiantString,SOV)
+            Newname = write_to_output(filename,ModifiedGS,overwrite)
+ 
+main_filehandler(True)

wally-pipelined/src/ifu/localHistoryPredictor.sv

@@ -43,7 +43,7 @@ module localHistoryPredictor
   
    );
 
-  logic [2**m-1:0][k-1:0]  LHRNextF;
+  logic [2**m-1:0]         [k-1:0]  LHRNextF;
   logic [k-1:0]            LHRF, ForwardLHRNext, LHRFNext;
   logic [m-1:0]            LookUpPCIndex, UpdatePCIndex;
   logic [1:0]              PredictionMemory;

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -154,9 +154,30 @@ module wallypipelinedhart (
   logic 		    BreakpointFaultM, EcallFaultM;
 
   
-  ifu ifu(.InstrInF(InstrRData),
-	  .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
-	  .*); // instruction fetch unit: PC, branch prediction, instruction cache
+  ifu ifu(
+    .clk, .reset, 
+    .StallF, .StallD, .StallE, .StallM, .StallW, 
+    .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, 
+    .InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, .InstrReadF, .ICacheStallF, 
+    .PCLinkE, .PCSrcE, .PCTargetE, .PCE,
+    .BPPredWrongE, 
+    .RetM, .TrapM, 
+    .PrivilegedNextPCM, .InvalidateICacheM,
+    .InstrD, .InstrM, 
+    .PCM, .InstrClassM, 
+    .BPPredDirWrongM,.BTBPredPCWrongM,.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
+    .IllegalBaseInstrFaultD, .ITLBInstrPageFaultF, .IllegalIEUInstrFaultD,
+    .InstrMisalignedFaultM, .InstrMisalignedAdrM,
+    .PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
+    .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+    .ITLBWriteF, .ITLBFlushF,
+    .WalkerInstrPageFaultF,
+    .ITLBMissF,
+    .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
+    .InstrAccessFaultF
+	  
+	  ); // instruction fetch unit: PC, branch prediction, instruction cache
+    
 
   ieu ieu(.*); // integer execution unit: integer register file, datapath and controller