diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 50951bd09..2630e0f76 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -44,6 +44,7 @@ module csr #(parameter input logic mretM, sretM, wfiM, // return or WFI instruction input logic IntPendingM, // at least one interrupt is pending and could occur if enabled input logic InterruptM, // interrupt is occurring + input logic ExceptionM, // interrupt is occurring input logic MTimerInt, // timer interrupt input logic MExtInt, SExtInt, // external interrupt (from PLIC) input logic MSwInt, // software interrupt @@ -68,6 +69,7 @@ module csr #(parameter input logic DCacheAccess, input logic ICacheMiss, input logic ICacheAccess, + input logic sfencevmaM, // outputs from CSRs output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, STATUS_TVM, @@ -258,9 +260,10 @@ module csr #(parameter if (`ZICOUNTERS_SUPPORTED) begin:counters csrc counters(.clk, .reset, .StallE, .StallM, .FlushM, - .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRMWriteM, + .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM, .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM, - .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, + .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM, + .InterruptM, .ExceptionM, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, .MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM); diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index 7a166effa..131be4ec6 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -43,7 +43,8 @@ module csrc #(parameter input logic clk, reset, input logic StallE, StallM, input logic FlushM, - input logic InstrValidNotFlushedM, LoadStallD, CSRMWriteM, StoreStallD, + input logic InstrValidNotFlushedM, LoadStallD, StoreStallD, + input logic CSRMWriteM, CSRWriteM, input logic BPDirPredWrongM, input logic BTBPredPCWrongM, input logic RASPredPCWrongM, @@ -54,6 +55,9 @@ module csrc #(parameter input logic DCacheAccess, input logic ICacheMiss, input logic ICacheAccess, + input logic sfencevmaM, + input logic InterruptM, + input logic ExceptionM, input logic [11:0] CSRAdrM, input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] CSRWriteValM, @@ -100,12 +104,12 @@ module csrc #(parameter assign CounterEvent[15] = '0; // //// ******* d cache miss cycles assign CounterEvent[16] = ICacheAccess & InstrValidNotFlushedM; // instruction cache access assign CounterEvent[17] = ICacheMiss; // instruction cache miss. Miss asserted 1 cycle at start of cache miss - assign CounterEvent[18] = '0; // //// ******** i cache miss cycles - assign CounterEvent[19] = '0; // ******** CSR writes + assign CounterEvent[18] = '0; // //// ******** i cache miss cycles + assign CounterEvent[19] = CSRWriteM & InstrValidNotFlushedM; // CSR writes assign CounterEvent[20] = '0; // ******** fence.i - assign CounterEvent[21] = '0; // ******** sfence.vma - assign CounterEvent[22] = '0; // ******** # interrupts - assign CounterEvent[23] = '0; // ******** # exceptions + assign CounterEvent[21] = sfencevmaM & InstrValidNotFlushedM; // sfence.vma + assign CounterEvent[22] = InterruptM; // interrupt, InstrValidNotFlushedM will be low + assign CounterEvent[23] = ExceptionM; // exceptions, InstrValidNotFlushedM will be low assign CounterEvent[24] = '0; // ******** # division cycles assign CounterEvent[`COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions end diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 5f6c17752..679d13bd6 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -106,9 +106,9 @@ module privileged ( logic DelegateM; // trap should be delegated logic wfiM; // wait for interrupt instruction logic IntPendingM; // interrupt is pending, even if not enabled. ends wfi - logic InterruptM; // interrupt occuring - - + logic InterruptM; // interrupt occuring + logic ExceptionM; // Memory stage instruction caused a fault + // track the current privilege level privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM, .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW); @@ -126,6 +126,7 @@ module privileged ( .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD, .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPWrongM, + .sfencevmaM, .ExceptionM, .IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM, @@ -149,7 +150,7 @@ module privileged ( .mretM, .sretM, .PrivilegeModeW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .InstrValidM, .CommittedM, .CommittedF, - .TrapM, .RetM, .wfiM, .InterruptM, .IntPendingM, .DelegateM, .WFIStallM, .CauseM); + .TrapM, .RetM, .wfiM, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .WFIStallM, .CauseM); endmodule diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index d8ad28f56..1d98763fc 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -45,6 +45,7 @@ module trap ( output logic TrapM, // Trap is occurring output logic RetM, // Return instruction being executed output logic InterruptM, // Interrupt is occurring + output logic ExceptionM, // exception is occurring output logic IntPendingM, // Interrupt is pending, might occur if enabled output logic DelegateM, // Delegate trap to supervisor handler output logic WFIStallM, // Stall due to WFI instruction @@ -52,7 +53,6 @@ module trap ( ); logic MIntGlobalEnM, SIntGlobalEnM; // Global interupt enables - logic ExceptionM; // exception is occurring logic Committed; // LSU or IFU has committed to a bus operation that can't be interrupted logic BothInstrAccessFaultM; // instruction or HPTW ITLB fill caused an Instruction Access Fault logic [11:0] PendingIntsM, ValidIntsM, EnabledIntsM; // interrupts are pending, valid, or enabled