Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/src/muldiv/muldiv.sv

@@ -52,7 +52,14 @@ module muldiv (
 	 logic           W64M; 
 	 
 	 // Multiplier
-	 mul mul(.*);
+	 mul mul(
+	 .clk, .reset,
+  	 .StallM, .FlushM,
+	    // .SrcAE, .SrcBE,
+	 .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
+	 .Funct3E,
+  	 .ProdM
+	 );
 
 	 // Divide
 	 // Start a divide when a new division instruction is received and the divider isn't already busy or finishing

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -316,9 +316,32 @@ module wallypipelinedhart (
 	       .*);
 
   
-  muldiv mdu(.*); // multiply and divide unit
+  muldiv mdu(
+    .clk, .reset,
+	       // Execute Stage interface
+	       //   .SrcAE, .SrcBE,
+		.ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
+	  .Funct3E, .Funct3M,
+	  .MulDivE, .W64E,
+	       // Writeback stage
+	  .MulDivResultW,
+	       // Divide Done
+	  .DivBusyE, 
+	       // hazards
+	  .StallM, .StallW, .FlushM, .FlushW 
+  ); // multiply and divide unit
   
-  hazard     hzu(.*);	// global stall and flush control
+  hazard     hzu(
+        .BPPredWrongE, .CSRWritePendingDEM, .RetM, .TrapM,
+        .LoadStallD, .StoreStallD, .MulDivStallD, .CSRRdStallD,
+	      .LSUStall, .ICacheStallF,
+        .FPUStallD, .FStallD,
+	      .DivBusyE, .FDivBusyE,
+	      .EcallFaultM, .BreakpointFaultM,
+        .InvalidateICacheM,
+  // Stall & flush outputs
+	      .StallF, .StallD, .StallE, .StallM, .StallW,
+	      .FlushF, .FlushD, .FlushE, .FlushM, .FlushW);	// global stall and flush control
 
   // Priveleged block operates in M and W stages, handling CSRs and exceptions
   privileged priv(.*);