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Removed unused signals

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This commit is contained in:
David Harris 2022-08-25 18:34:39 -07:00
parent b73286ece6
commit f262abb5c3
2 changed files with 4 additions and 8 deletions
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5
pipelined/src/lsu/busfsm.sv
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@ -43,9 +43,7 @@ module busfsm #(parameter integer LOGWPL)
output logic BusStall, output logic BusStall,
output logic BusWrite, output logic BusWrite,
output logic SelBusWord,
output logic BusRead, output logic BusRead,
output logic BusTransComplete,
output logic [1:0] HTRANS, output logic [1:0] HTRANS,
output logic BusCommitted output logic BusCommitted
); );
@ -85,7 +83,6 @@ module busfsm #(parameter integer LOGWPL)
endcase endcase
end end
assign BusTransComplete = BusAck;
assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & |RW) | assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & |RW) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) |
(BusCurrState == STATE_BUS_UNCACHED_READ); (BusCurrState == STATE_BUS_UNCACHED_READ);
@ -94,8 +91,6 @@ module busfsm #(parameter integer LOGWPL)
assign BusRead = (BusCurrState == STATE_BUS_READY & RW[1] & ~IgnoreRequest) | assign BusRead = (BusCurrState == STATE_BUS_READY & RW[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ); (BusCurrState == STATE_BUS_UNCACHED_READ);
assign BusCommitted = BusCurrState != STATE_BUS_READY; assign BusCommitted = BusCurrState != STATE_BUS_READY;
assign SelBusWord = (BusCurrState == STATE_BUS_READY & RW[0]) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE);
assign HTRANS = (BusRead | BusWrite) & (~BusAck) ? AHB_NONSEQ : AHB_IDLE; assign HTRANS = (BusRead | BusWrite) & (~BusAck) ? AHB_NONSEQ : AHB_IDLE;
endmodule endmodule

7
pipelined/src/lsu/lsu.sv
View File

@ -108,7 +108,6 @@ module lsu (
logic InterlockStall; logic InterlockStall;
logic IgnoreRequestTLB; logic IgnoreRequestTLB;
logic BusCommittedM, DCacheCommittedM; logic BusCommittedM, DCacheCommittedM;
logic SelBusWord;
logic DataDAPageFaultM; logic DataDAPageFaultM;
logic [`XLEN-1:0] IMWriteDataM, IMAWriteDataM; logic [`XLEN-1:0] IMWriteDataM, IMAWriteDataM;
logic [`LLEN-1:0] IMAFWriteDataM; logic [`LLEN-1:0] IMAFWriteDataM;
@ -224,6 +223,7 @@ module lsu (
if(`DCACHE) begin : dcache if(`DCACHE) begin : dcache
logic SelUncachedAdr, DCacheBusAck; logic SelUncachedAdr, DCacheBusAck;
logic SelBusWord;
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
@ -257,12 +257,13 @@ module lsu (
busfsm #(LOGBWPL) busfsm( busfsm #(LOGBWPL) busfsm(
.clk, .reset, .IgnoreRequest, .RW(LSURWM), .clk, .reset, .IgnoreRequest, .RW(LSURWM),
.BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .BusStall, .BusWrite(LSUBusWrite), .BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .BusStall, .BusWrite(LSUBusWrite),
.SelBusWord, .BusRead(LSUBusRead), .BusRead(LSUBusRead),
.HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), .HTRANS(LSUHTRANS),
.BusCommitted(BusCommittedM)); .BusCommitted(BusCommittedM));
// *** possible bug - ReadDatWordM vs. ReadDataWordMuxW - is byte swapping needed for endian // *** possible bug - ReadDatWordM vs. ReadDataWordMuxW - is byte swapping needed for endian
assign LSUHBURST = 3'b0; assign LSUHBURST = 3'b0;
assign LSUTransComplete = BusAck;
assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0; assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;
assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM; assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM;
end end