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Replacement policy cleanup.

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This commit is contained in:
Ross Thompson 2022-02-10 11:42:40 -06:00
parent 411997010b
commit f23817bf69
1 changed files with 13 additions and 14 deletions
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27
pipelined/src/cache/cachereplacementpolicy.sv vendored
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@ -30,31 +30,30 @@
`include "wally-config.vh" `include "wally-config.vh"
module cachereplacementpolicy module cachereplacementpolicy
#(parameter NUMWAYS = 4, INDEXLEN = 9, OFFSETLEN = 5, NUMLINES = 128)( #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128)(
input logic clk, reset, input logic clk, reset,
input logic [NUMWAYS-1:0] WayHit, input logic [NUMWAYS-1:0] WayHit,
output logic [NUMWAYS-1:0] VictimWay, output logic [NUMWAYS-1:0] VictimWay,
input logic [`PA_BITS-1:0] PAdr, input logic [`PA_BITS-1:0] PAdr,
input logic [INDEXLEN-1:0] RAdr, input logic [SETLEN-1:0] RAdr,
input logic LRUWriteEn); input logic LRUWriteEn);
logic [NUMWAYS-2:0] LRUEn, LRUMask; logic [NUMWAYS-2:0] LRUEn, LRUMask;
logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0]; logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0];
logic [NUMWAYS-2:0] LineReplacementBits; logic [NUMWAYS-2:0] LineReplacementBits;
logic [NUMWAYS-2:0] NewReplacement; logic [NUMWAYS-2:0] NewReplacement;
logic [NUMWAYS-2:0] NewReplacementD; logic [NUMWAYS-2:0] NewReplacementD;
logic [SETLEN+OFFSETLEN-1:OFFSETLEN] PAdrD;
logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] PAdrD; logic [SETLEN-1:0] RAdrD;
logic [INDEXLEN-1:0] RAdrD; logic LRUWriteEnD;
logic LRUWriteEnD;
initial begin initial begin
assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported"); assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported");
end end
// Pipeline Delay Registers // Pipeline Delay Registers
flopr #(INDEXLEN) RAdrDelayReg(clk, reset, RAdr, RAdrD); flopr #(SETLEN) RAdrDelayReg(clk, reset, RAdr, RAdrD);
flopr #(INDEXLEN) PAdrDelayReg(clk, reset, PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN], PAdrD); flopr #(SETLEN) PAdrDelayReg(clk, reset, PAdr[SETLEN+OFFSETLEN-1:OFFSETLEN], PAdrD);
flopr #(1) LRUWriteEnDelayReg(clk, reset, LRUWriteEn, LRUWriteEnD); flopr #(1) LRUWriteEnDelayReg(clk, reset, LRUWriteEn, LRUWriteEnD);
flopr #(NUMWAYS-1) NewReplacementDelayReg(clk, reset, NewReplacement, NewReplacementD); flopr #(NUMWAYS-1) NewReplacementDelayReg(clk, reset, NewReplacement, NewReplacementD);
@ -62,7 +61,7 @@ module cachereplacementpolicy
// Needs to be resettable for simulation, but could omit reset for synthesis *** // Needs to be resettable for simulation, but could omit reset for synthesis ***
always_ff @(posedge clk) always_ff @(posedge clk)
if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] = '0; if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] = '0;
else if (LRUWriteEnD) ReplacementBits[PAdrD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] = NewReplacementD; else if (LRUWriteEnD) ReplacementBits[PAdrD[SETLEN+OFFSETLEN-1:OFFSETLEN]] = NewReplacementD;
assign LineReplacementBits = ReplacementBits[RAdrD]; assign LineReplacementBits = ReplacementBits[RAdrD];
genvar index; genvar index;