diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc index 638cfb2a5..3fbb95f68 100644 --- a/fpga/constraints/constraints-vcu108.xdc +++ b/fpga/constraints/constraints-vcu108.xdc @@ -1,12 +1,8 @@ # The main clocks are all autogenerated by the Xilinx IP -# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus. +# mmcm_clkout1 is the 50Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus. # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. -# create_generated_clock -name CLKDiv64_Gen -source [get_pins #wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] -#create_generated_clock -name CLKDiv64_Gen -source [get_pins ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q] -create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK] - ##### GPI #### set_property PACKAGE_PIN E34 [get_ports {GPI[0]}] set_property PACKAGE_PIN M22 [get_ports {GPI[1]}] @@ -86,13 +82,14 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port ##### SD Card I/O ##### -set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}] -set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}] -set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}] -set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}] -set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK] +# create the generated SPICLK +#create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/spi.spi/SPICLK] + +set_output_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCCS}] +set_input_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCIn}] +set_output_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks mmcm_clkout1] 0.000 [get_ports SDCCLK] + set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}] set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCIn}] @@ -107,17 +104,9 @@ set_property PACKAGE_PIN BC16 [get_ports SDCWP] set_property IOSTANDARD LVCMOS18 [get_ports SDCWP] set_property PULLTYPE PULLUP [get_ports SDCWP] -#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] -#set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}] -#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}] -#set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}] -#set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}] -#set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}] -#set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK] - -set_property DCI_CASCADE {64} [get_iobanks 65] +#set_property DCI_CASCADE {64} [get_iobanks 65] set_property INTERNAL_VREF 0.9 [get_iobanks 65] diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 1d23c29a2..87d470a33 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -5,3 +5,15 @@ wally/wallypipelinedcore.sv: logic InstrM lsu/lsu.sv: logic IEUAdrM lsu/lsu.sv: logic MemRWM mmu/hptw.sv: logic SATP_REGW +uncore/spi_apb.sv: logic ShiftIn +uncore/spi_apb.sv: logic ReceiveShiftReg +uncore/spi_apb.sv: logic SCLKenable +uncore/spi_apb.sv: logic SampleEdge +uncore/spi_apb.sv: logic Active +uncore/spi_apb.sv: statetype state +uncore/spi_apb.sv: typedef rsrstatetype +uncore/spi_apb.sv: logic SPICLK +uncore/spi_apb.sv: logic SPIOut +uncore/spi_apb.sv: logic SPICS +uncore/spi_apb.sv: logic SckMode +uncore/spi_apb.sv: logic SckDiv diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 106345854..9c1a3f496 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -10,6 +10,11 @@ set board $::env(board) #set boardSubName arty-a7-100 #set board ArtyA7 +set partNumber xcvu095-ffva2104-2-e +set boardName xilinx.com:vcu108:part0:1.7 +set boardSubName vcu108 +set board FPU_VCU + set ipName WallyFPGA create_project $ipName . -force -part $partNumber @@ -55,6 +60,13 @@ update_compile_order -fileset sources_1 exec mkdir -p reports/ exec rm -rf reports/* + +report_compile_order -constraints > reports/compile_order.rpt + +# this is elaboration not synthesis. +synth_design -rtl -name rtl_1 -flatten_hierarchy none + +# apply timing constraint after elaboration if {$board=="ArtyA7"} { add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc] @@ -63,11 +75,6 @@ if {$board=="ArtyA7"} { set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc] } -report_compile_order -constraints > reports/compile_order.rpt - -# this is elaboration not synthesis. -synth_design -rtl -name rtl_1 -flatten_hierarchy none - report_clocks -file reports/clocks.rpt # Temp @@ -94,7 +101,8 @@ if {$board=="ArtyA7"} { #source ../constraints/small-debug-rvvi.xdc } else { #source ../constraints/vcu-small-debug.xdc - source ../constraints/small-debug.xdc + #source ../constraints/small-debug.xdc + source ../constraints/small-debug-spi.xdc } diff --git a/linux/devicetree/wally-vcu108.dts b/linux/devicetree/wally-vcu108.dts index ef3694066..01deddc6e 100644 --- a/linux/devicetree/wally-vcu108.dts +++ b/linux/devicetree/wally-vcu108.dts @@ -102,7 +102,7 @@ mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; voltage-ranges = <3300 3300>; disable-wp; // gpios = <&gpio0 6 1>;