From 52d4a04eb0b4605549477bca254663040c5e240b Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 8 Mar 2021 09:38:55 -0500 Subject: [PATCH 1/7] Created atomic test vector and directories --- wally-pipelined/src/ebu/ahblite.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 10aa1f1ae..ad604be54 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -102,7 +102,7 @@ module ahblite ( else NextBusState = IDLE; INSTRREAD: //if (~HREADY & (MemReadM | MemWriteM)) NextBusState = INSTRREADMEMPENDING; // *** shouldn't happen, delete if (~HREADY) NextBusState = INSTRREAD; - else NextBusState = IDLE; + else NextBusState = IDLE; // if (InstrReadF still high) INSTRREADMEMPENDING: if (~HREADY) NextBusState = INSTRREADMEMPENDING; // *** shouldn't happen, delete else if (MemReadM) NextBusState = MEMREAD; else NextBusState = MEMWRITE; // must be write if not a read. Don't return to idle. From 1fc00d41c2931ea9f1044dbd4066be2b16d36079 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Mon, 8 Mar 2021 19:26:26 +0000 Subject: [PATCH 2/7] busybear: load mem files from verilog instead of .do --- wally-pipelined/regression/wally-busybear.do | 9 --------- wally-pipelined/testbench/testbench-busybear.sv | 8 ++++++++ 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 271b8237a..7e0fd66b1 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -42,15 +42,6 @@ switch $argc { 1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory} } -mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/bootdtim/RAM -mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/uncore/bootdtim/RAM -mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/bootram -mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/imem/bootram -mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/dtim/RAM -mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/uncore/dtim/RAM -mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/RAM -mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/imem/RAM - view wave diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index e6ba95a13..ba554e533 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -95,6 +95,14 @@ module testbench_busybear(); end end + // initial loading of memories + initial begin + $readmemh("/courses/e190ax/busybear_boot/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3); + $readmemh("/courses/e190ax/busybear_boot/ram.txt", dut.uncore.dtim.RAM); + $readmemh("/courses/e190ax/busybear_boot/bootmem.txt", dut.imem.bootram, 'h1000 >> 3); + $readmemh("/courses/e190ax/busybear_boot/ram.txt", dut.imem.RAM); + end + integer warningCount = 0; //logic[63:0] adrTranslation[4:0]; From 08e3691e59884be87cd0da48bf4bdc1904efa6c5 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Mon, 8 Mar 2021 19:35:00 +0000 Subject: [PATCH 3/7] busybear: make a second .do file with better optimization for command line mode --- wally-pipelined/regression/sim-busybear-batch | 2 +- .../regression/wally-busybear-batch.do | 46 +++++++++++++++++++ 2 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 wally-pipelined/regression/wally-busybear-batch.do diff --git a/wally-pipelined/regression/sim-busybear-batch b/wally-pipelined/regression/sim-busybear-batch index 2c351aade..194863b4f 100755 --- a/wally-pipelined/regression/sim-busybear-batch +++ b/wally-pipelined/regression/sim-busybear-batch @@ -1,3 +1,3 @@ vsim -c <" prompt: +# do wally-pipelined.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work-busybear] { + vdel -all -lib work-busybear +} +vlib work-busybear + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt +vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 + + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vopt +acc=+/testbench_busybear/dut/hart/ifu/bpred/DirPredictor/memory/memory +acc=+/testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory work.testbench_busybear -o workopt + +vsim workopt -suppress 8852,12070 +# load the branch predictors with known data. The value of the data is not important for function, but +# is important for perventing pessimistic x propagation. +mem load -infile twoBitPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/DirPredictor/memory/memory +switch $argc { + 0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory} + 1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory} +} + +run -all +quit From 9274d09ae295981ece8a17974bb240ccf90b8879 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Mon, 8 Mar 2021 19:48:12 +0000 Subject: [PATCH 4/7] busybear: better instrF checking So this now checks instrF only when StallD is low. @kaveh I'd love your opinion on this. I don't know if this is a good idea or not. Ideally we should probably be checking InstrRawD instead, but I kind of want to stay checking the instr in the F stage instead of D for now. Idk if this is worth staying in F, I can't really see any big downsides to checking the instruction in D except that PCD isn't an external signal, but neither is StallD, so..... Anyway I'd love others' thoughts on this --- wally-pipelined/regression/wally-busybear.do | 190 +++++++++--------- .../testbench/testbench-busybear.sv | 10 +- 2 files changed, 101 insertions(+), 99 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 7e0fd66b1..42d04cb77 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -1,37 +1,37 @@ -# wally-pipelined.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with testbench_busybear -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work-busybear] { - vdel -all -lib work-busybear -} -vlib work-busybear - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt +# wally-pipelined.do +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with testbench_busybear +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# Use this wally-pipelined.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-pipelined.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work-busybear] { + vdel -all -lib work-busybear +} +vlib work-busybear + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt +acc work.testbench_busybear -o workopt + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vopt +acc work.testbench_busybear -o workopt vsim workopt -suppress 8852,12070 # load the branch predictors with known data. The value of the data is not important for function, but @@ -42,31 +42,33 @@ switch $argc { 1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory} } - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave /testbench_busybear/clk -add wave /testbench_busybear/reset -add wave -divider + +view wave + +-- display input and output signals as hexidecimal values +# Diplays All Signals recursively +add wave /testbench_busybear/clk +add wave /testbench_busybear/reset +add wave -divider add wave -hex /testbench_busybear/PCtext add wave -hex /testbench_busybear/pcExpected -add wave -hex /testbench_busybear/dut/hart/ifu/PCF -add wave -hex /testbench_busybear/dut/hart/ifu/InstrF -add wave -hex /testbench_busybear/dut/InstrF +add wave -hex /testbench_busybear/dut/hart/ifu/PCF +add wave -hex /testbench_busybear/dut/hart/ifu/InstrF +add wave -hex /testbench_busybear/dut/hart/ifu/StallD +add wave -hex /testbench_busybear/dut/hart/ifu/FlushD +add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD add wave /testbench_busybear/CheckInstrF add wave /testbench_busybear/lastCheckInstrF add wave /testbench_busybear/speculative add wave /testbench_busybear/lastPC2 -add wave -divider -add wave -divider +add wave -divider +add wave -divider add wave /testbench_busybear/dut/uncore/HSELBootTim add wave /testbench_busybear/dut/uncore/HSELTim add wave /testbench_busybear/dut/uncore/HREADTim add wave /testbench_busybear/dut/uncore/dtim/HREADTim0 add wave /testbench_busybear/dut/uncore/HREADYTim -add wave -divider +add wave -divider add wave /testbench_busybear/dut/uncore/HREADBootTim add wave /testbench_busybear/dut/uncore/bootdtim/HREADTim0 add wave /testbench_busybear/dut/uncore/HREADYBootTim @@ -80,8 +82,8 @@ add wave /testbench_busybear/dut/uncore/HRDATA #add wave -hex /testbench_busybear/dut/hart/priv/csr/MIE_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MIDELEG_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MEDELEG_REG -add wave -divider -# registers! +add wave -divider +# registers! add wave -hex /testbench_busybear/regExpected add wave -hex /testbench_busybear/regNumExpected add wave -hex /testbench_busybear/HWRITE @@ -121,49 +123,49 @@ add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[28] add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[29] add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[30] add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[31] -add wave /testbench_busybear/InstrFName -add wave -hex /testbench_busybear/dut/hart/ifu/PCD -#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD -add wave /testbench_busybear/InstrDName -#add wave -divider -add wave -hex /testbench_busybear/dut/hart/ifu/PCE -##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE -add wave /testbench_busybear/InstrEName -#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE -#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE -add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE -#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE -#add wave -divider -add wave -hex /testbench_busybear/dut/hart/ifu/PCM -##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM -add wave /testbench_busybear/InstrMName -#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite -#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM -#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM -#add wave -divider -add wave -hex /testbench_busybear/dut/hart/ifu/PCW -##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW -add wave /testbench_busybear/InstrWName -#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW -#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW -#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW -#add wave -divider -##add ww -add wave -hex -r /testbench_busybear/* -# -#-- Set Wave Output Items -#TreeUpdate [SetDefaultTree] -#WaveRestoreZoom {0 ps} {100 ps} -#configure wave -namecolwidth 250 -#configure wave -valuecolwidth 120 -#configure wave -justifyvalue left -#configure wave -signalnamewidth 0 -#configure wave -snapdistance 10 -#configure wave -datasetprefix 0 -#configure wave -rowmargin 4 -#configure wave -childrowmargin 2 -#set DefaultRadix hexadecimal -# -#-- Run the Simulation -run -all -##quit +add wave /testbench_busybear/InstrFName +add wave -hex /testbench_busybear/dut/hart/ifu/PCD +#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD +add wave /testbench_busybear/InstrDName +#add wave -divider +add wave -hex /testbench_busybear/dut/hart/ifu/PCE +##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE +add wave /testbench_busybear/InstrEName +#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE +#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE +add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE +#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE +#add wave -divider +add wave -hex /testbench_busybear/dut/hart/ifu/PCM +##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM +add wave /testbench_busybear/InstrMName +#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite +#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM +#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM +#add wave -divider +add wave -hex /testbench_busybear/dut/hart/ifu/PCW +##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW +add wave /testbench_busybear/InstrWName +#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW +#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW +#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW +#add wave -divider +##add ww +add wave -hex -r /testbench_busybear/* +# +#-- Set Wave Output Items +#TreeUpdate [SetDefaultTree] +#WaveRestoreZoom {0 ps} {100 ps} +#configure wave -namecolwidth 250 +#configure wave -valuecolwidth 120 +#configure wave -justifyvalue left +#configure wave -signalnamewidth 0 +#configure wave -snapdistance 10 +#configure wave -datasetprefix 0 +#configure wave -rowmargin 4 +#configure wave -childrowmargin 2 +#set DefaultRadix hexadecimal +# +#-- Run the Simulation +run -all +##quit diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index ba554e533..6b54abf6d 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -162,10 +162,10 @@ module testbench_busybear(); $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); `ERROR end - if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin - force dut.hart.ieu.dp.regf.rf[i] = regExpected; - release dut.hart.ieu.dp.regf.rf[i]; - end + //if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin + // force dut.hart.ieu.dp.regf.rf[i] = regExpected; + // release dut.hart.ieu.dp.regf.rf[i]; + //end end end end @@ -348,7 +348,7 @@ module testbench_busybear(); always @(dut.PCF or dut.hart.ifu.InstrF or reset) begin if(~HWRITE) begin #3; - if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}}) begin + if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}} && ~dut.hart.StallD) begin if (dut.PCF !== lastPCF) begin lastCheckInstrF = CheckInstrF; lastPC <= dut.PCF; From 87e2a9b9204524ea2167c10811756ff3a5befb05 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Mon, 8 Mar 2021 21:24:19 +0000 Subject: [PATCH 5/7] busybear: better NOPing out of float instructions --- .../testbench/testbench-busybear.sv | 65 +++++++++++++++---- 1 file changed, 51 insertions(+), 14 deletions(-) diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 6b54abf6d..e4c9c9e39 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -187,8 +187,8 @@ module testbench_busybear(); logic [`XLEN-1:0] readAdrExpected; - always @(dut.hart.MemRWM[1] or HADDR) begin - if (dut.hart.MemRWM[1] && HADDR != dut.PCF) begin + always @(dut.hart.MemRWM[1] or HADDR or dut.HRDATA) begin + if (dut.hart.MemRWM[1] && HADDR != dut.PCF && dut.HRDATA != {64{1'bx}}) begin if($feof(data_file_memR)) begin $display("no more memR data to read"); `ERROR @@ -202,7 +202,7 @@ module testbench_busybear(); end if (((readMask & HRDATA) !== (readMask & dut.HRDATA)) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin - $display("warning %0t ps, instr %0d: HRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE); + $display("warning %0t ps, instr %0d: ExpectedHRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE); warningCount += 1; `ERROR end @@ -355,6 +355,33 @@ module testbench_busybear(); lastPC2 <= lastPC; if (speculative && (lastPC != pcExpected)) begin speculative = ~equal(dut.PCF,pcExpected,3); + if(dut.PCF===pcExpected) begin + if(dut.hart.ifu.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs + force CheckInstrF = 32'b0010011; + release CheckInstrF; + force dut.hart.ifu.InstrF = 32'b0010011; + #7; + release dut.hart.ifu.InstrF; + $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time); + warningCount += 1; + forcedInstr = 1; + end + else begin + if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD + force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011}; + release CheckInstrF; + force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011}; + #7; + release dut.hart.ifu.InstrF; + $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF); + warningCount += 1; + forcedInstr = 1; + end + else begin + forcedInstr = 0; + end + end + end end else begin if($feof(data_file_PC)) begin @@ -367,21 +394,31 @@ module testbench_busybear(); PCtext = {PCtext, " ", PCtext2}; end scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrF); - if(CheckInstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs - CheckInstrF = 32'b0010011; - $display("warning: NOPing out %s at PC=%0x", PCtext, dut.PCF); - warningCount += 1; - forcedInstr = 1; - end - else begin - if(CheckInstrF[28:27] != 2'b11 && CheckInstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD - CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011}; - $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF); + if(dut.PCF === pcExpected) begin + if(dut.hart.ifu.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs + force CheckInstrF = 32'b0010011; + release CheckInstrF; + force dut.hart.ifu.InstrF = 32'b0010011; + #7; + release dut.hart.ifu.InstrF; + $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time); warningCount += 1; forcedInstr = 1; end else begin - forcedInstr = 0; + if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD + force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011}; + release CheckInstrF; + force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011}; + #7; + release dut.hart.ifu.InstrF; + $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF); + warningCount += 1; + forcedInstr = 1; + end + else begin + forcedInstr = 0; + end end end // then expected PC value From bea8ac6d59c0b80e27c4962f0327a74eb0e99933 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 9 Mar 2021 09:28:25 -0500 Subject: [PATCH 6/7] WALLY-LRSC atomic test passing --- wally-pipelined/config/rv64ic/wally-config.vh | 4 +-- wally-pipelined/regression/wally-pipelined.do | 2 +- wally-pipelined/src/dmem/dmem.sv | 2 +- wally-pipelined/src/ieu/controller.sv | 2 +- .../testbench/testbench-imperas.sv | 36 +++++++++++++++++-- 5 files changed, 38 insertions(+), 8 deletions(-) diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 4a9c303d4..e5240e8ba 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -27,8 +27,8 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 -//`define MISA (32'h00000104) -`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12) +//`define MISA (32'h00000105) +`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0) `define A_SUPPORTED ((`MISA >> 0) % 2 == 1) `define C_SUPPORTED ((`MISA >> 2) % 2 == 1) `define D_SUPPORTED ((`MISA >> 3) % 2 == 1) diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do index 813374ef7..94a2bef28 100644 --- a/wally-pipelined/regression/wally-pipelined.do +++ b/wally-pipelined/regression/wally-pipelined.do @@ -113,6 +113,6 @@ configure wave -childrowmargin 2 set DefaultRadix hexadecimal -- Run the Simulation -#run 2000 +#run 4100 run -all #quit diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index aa4327c21..547663fce 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -100,7 +100,7 @@ module dmem ( assign lrM = MemReadM && AtomicM; assign scM = MemRWM[0] && AtomicM; - assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM == ReservationPAdrW) && ReservationValidW; + assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`XLEN-1:2] == ReservationPAdrW) && ReservationValidW; assign SquashSCM = scM && ~WriteAdrMatchM; always_comb begin // ReservationValidM (next valiue of valid reservation) if (lrM) ReservationValidM = 1; // set valid on load reserve diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index 7721dc919..dc4f16d5b 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -116,7 +116,7 @@ module controller( if (InstrD[31:27] == 5'b00010) ControlsD = 22'b1_000_00_10_001_0_00_0_0_0_0_0_0_1_0; // lr else if (InstrD[31:27] == 5'b00011) - ControlsD = 22'b1_101_01_01_110_0_00_0_0_0_0_0_0_1_0; // sc + ControlsD = 22'b1_101_01_01_101_0_00_0_0_0_0_0_0_1_0; // sc else ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_0_0_1_0; // other atomic; decode later end else diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 78ee58102..50ef7c93b 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -37,6 +37,9 @@ module testbench(); string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; //logic [31:0] InstrW; logic [`XLEN-1:0] meminit; + string tests64a[] = '{ + "rv64a/WALLY-LRSC", "2110" + }; string tests64m[] = '{ "rv64m/I-MUL-01", "3000", "rv64m/I-MULH-01", "3000", @@ -322,9 +325,11 @@ string tests32i[] = { initial if (`XLEN == 64) begin // RV64 tests = {tests64i}; - if (`C_SUPPORTED % 2 == 1) tests = {tests, tests64ic}; - else tests = {tests, tests64iNOc}; - if (`M_SUPPORTED % 2 == 1) tests = {tests, tests64m}; + if (`C_SUPPORTED) tests = {tests, tests64ic}; + else tests = {tests, tests64iNOc}; + if (`M_SUPPORTED) tests = {tests, tests64m}; + if (`A_SUPPORTED) tests = {tests64a, tests}; + // tests = {tests64a, tests}; end else begin // RV32 tests = {tests32i}; if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic}; @@ -368,6 +373,7 @@ string tests32i[] = { memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); + $display("Read memfile %s", memfilename); reset = 1; # 42; reset = 0; end @@ -584,6 +590,30 @@ module instrNameDecTB( 10'b1110011_101: name = "CSRRWI"; 10'b1110011_110: name = "CSRRSI"; 10'b1110011_111: name = "CSRRCI"; + 10'b0101111_010: if (funct7[6:2] == 5'b00010) name = "LR.W"; + else if (funct7[6:2] == 5'b00011) name = "SC.W"; + else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W"; + else if (funct7[6:2] == 5'b00000) name = "AMOADD.W"; + else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W"; + else if (funct7[6:2] == 5'b01100) name = "AMOAND.W"; + else if (funct7[6:2] == 5'b01000) name = "AMOOR.W"; + else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W"; + else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W"; + else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W"; + else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W"; + else name = "ILLEGAL"; + 10'b0101111_011: if (funct7[6:2] == 5'b00010) name = "LR.D"; + else if (funct7[6:2] == 5'b00011) name = "SC.D"; + else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D"; + else if (funct7[6:2] == 5'b00000) name = "AMOADD.D"; + else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D"; + else if (funct7[6:2] == 5'b01100) name = "AMOAND.D"; + else if (funct7[6:2] == 5'b01000) name = "AMOOR.D"; + else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D"; + else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D"; + else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D"; + else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D"; + else name = "ILLEGAL"; 10'b0001111_???: name = "FENCE"; default: name = "ILLEGAL"; endcase From 2d1f63b5908d8a9d1c30b048691cee3a3a43a845 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Wed, 10 Mar 2021 19:14:02 +0000 Subject: [PATCH 7/7] change flop in ahb controller to use normal flop module --- wally-pipelined/src/ebu/ahblite.sv | 4 +--- wally-pipelined/src/generic/flop.sv | 10 +++++----- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index ad604be54..07918cdb2 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -84,9 +84,7 @@ module ahblite ( typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADMEMPENDING} statetype; statetype BusState, NextBusState; - always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) BusState <= #1 IDLE; - else BusState <= #1 NextBusState; + flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); always_comb case (BusState) diff --git a/wally-pipelined/src/generic/flop.sv b/wally-pipelined/src/generic/flop.sv index 7e954a8f8..a5636c6f4 100644 --- a/wally-pipelined/src/generic/flop.sv +++ b/wally-pipelined/src/generic/flop.sv @@ -82,11 +82,11 @@ module flopenr #(parameter WIDTH = 8) ( endmodule // flop with enable, asynchronous load -module flopenl #(parameter WIDTH = 8) ( - input logic clk, load, en, - input logic [WIDTH-1:0] d, - input logic [WIDTH-1:0] val, - output logic [WIDTH-1:0] q); +module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( + input logic clk, load, en, + input TYPE d, + input TYPE val, + output TYPE q); always_ff @(posedge clk, posedge load) if (load) q <= #1 val;