From f1f21f089657f5e2a8527af148ebf8ccab8cb31b Mon Sep 17 00:00:00 2001
From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com>
Date: Mon, 12 Jun 2023 13:31:54 -0700
Subject: [PATCH] Update subwordread.sv

Program clean up
---
 src/lsu/subwordread.sv | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv
index 4c529ec07..e5666eb84 100644
--- a/src/lsu/subwordread.sv
+++ b/src/lsu/subwordread.sv
@@ -29,12 +29,12 @@
 
 module subwordread #(parameter LLEN) 
   (
-   input logic [LLEN-1:0]  ReadDataWordMuxM,
+   input logic [LLEN-1:0]   ReadDataWordMuxM,
    input logic [2:0]        PAdrM,
    input logic [2:0]        Funct3M,
    input logic              FpLoadStoreM, 
    input logic              BigEndianM, 
-   output logic [LLEN-1:0] ReadDataM
+   output logic [LLEN-1:0]  ReadDataM
 );
 
   logic [7:0]               ByteM; 
@@ -89,7 +89,7 @@ module subwordread #(parameter LLEN)
     //3'b100:  ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq   - only needed when LLEN=128
       3'b101:  ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]};                       // lhu
       3'b110:  ReadDataM = {{LLEN-32{1'b0}}, WordM[31:0]};                           // lwu
-      default: ReadDataM = ReadDataWordMuxM;                                          // Shouldn't happen
+      default: ReadDataM = ReadDataWordMuxM;                                         // Shouldn't happen
     endcase
 
   end else begin:swrmux // 32-bit