Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Update ieu.sv

Browse Source 
Program clean up
This commit is contained in:
Harshini Srinath 2023-06-12 12:19:04 -07:00 committed by GitHub
parent 304adcb9b0
commit f1cef043c6
1 changed files with 13 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/ieu/ieu.sv
View File

@ -26,7 +26,6 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module ieu import cvw::*; #(parameter cvw_t P) ( module ieu import cvw::*; #(parameter cvw_t P) (
input logic clk, reset, input logic clk, reset,
// Decode stage signals // Decode stage signals
@ -53,7 +52,7 @@ module ieu import cvw::*; #(parameter cvw_t P) (
output logic [4:0] RdM, // Destination register output logic [4:0] RdM, // Destination register
input logic [P.XLEN-1:0] FIntResM, // Integer result from FPU (fmv, fclass, fcmp) input logic [P.XLEN-1:0] FIntResM, // Integer result from FPU (fmv, fclass, fcmp)
output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
output logic InstrValidD, InstrValidE, InstrValidM,// Instruction is valid output logic InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
output logic BranchD, BranchE, output logic BranchD, BranchE,
output logic JumpD, JumpE, output logic JumpD, JumpE,
// Writeback stage signals // Writeback stage signals
@ -118,4 +117,3 @@ module ieu import cvw::*; #(parameter cvw_t P) (
.FCvtIntE, .SCE, .ForwardAE, .ForwardBE, .FCvtIntE, .SCE, .ForwardAE, .ForwardBE,
.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD); .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD);
endmodule endmodule