From f143518b232cc30f57c83af8c35c66942ba1022a Mon Sep 17 00:00:00 2001 From: Jarred Allen Date: Mon, 1 Feb 2021 23:29:03 -0500 Subject: [PATCH] Fix issues in parallel regression testing --- .../regression/regression-wally.py | 2 +- .../wally-pipelined-batch-parallel.do | 38 +++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 wally-pipelined/regression/wally-pipelined-batch-parallel.do diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index d8f2489e6..f97202d4d 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -18,7 +18,7 @@ fail = 0 def test_config(config, print_res=True): """Run the given config, and return 0 if it suceeds and 1 if it fails""" logname = "wally_"+config+".log" - cmd = "vsim -c >" + logname +" <" + logname +" <" prompt: +# do wally-pipelined.do ../config/rv64ic +# or, to run from a shell, type the following at the shell prompt: +# vsim -c -do wally-pipelined.do ../config/rv64ic +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work$2 + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt +vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583 + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vopt work.testbench -o workopt +vsim workopt + +run -all +quit