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Preemptively fixed the bytemask bug before testing.

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This commit is contained in:
Rose Thompson 2023-10-30 15:47:46 -05:00
parent b5763e11e8
commit f13b67b869
4 changed files with 21 additions and 11 deletions
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2
src/ebu/ahbcacheinterface.sv
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@ -113,7 +113,7 @@ module ahbcacheinterface #(
// *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
// probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM)); swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended());
flopen #(AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[AHBW/8-1:0], HWSTRB); flopen #(AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[AHBW/8-1:0], HWSTRB);

5
src/lsu/align.sv
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@ -44,6 +44,7 @@ module align import cvw::*; #(parameter cvw_t P) (
input logic DataUpdateDAM, // ITLB miss, ignore memory request input logic DataUpdateDAM, // ITLB miss, ignore memory request
input logic [(P.LLEN-1)/8:0] ByteMaskM, input logic [(P.LLEN-1)/8:0] ByteMaskM,
input logic [(P.LLEN-1)/8:0] ByteMaskExtendedM,
input logic [P.LLEN-1:0] LSUWriteDataM, input logic [P.LLEN-1:0] LSUWriteDataM,
output logic [(P.LLEN*2-1)/8:0] ByteMaskSpillM, output logic [(P.LLEN*2-1)/8:0] ByteMaskSpillM,
@ -156,7 +157,7 @@ module align import cvw::*; #(parameter cvw_t P) (
assign LSUWriteDataShiftedM = {LSUWriteDataM, LSUWriteDataM} << (MisalignedM ? 8 * ByteOffsetM : '0); assign LSUWriteDataShiftedM = {LSUWriteDataM, LSUWriteDataM} << (MisalignedM ? 8 * ByteOffsetM : '0);
mux2 #(2*P.LLEN) writedataspillmux(LSUWriteDataShiftedM, {{{P.LLEN}{1'b0}}, LSUWriteDataShiftedM[P.LLEN*2-1:P.LLEN]}, SelSpillM, LSUWriteDataSpillM); mux2 #(2*P.LLEN) writedataspillmux(LSUWriteDataShiftedM, {{{P.LLEN}{1'b0}}, LSUWriteDataShiftedM[P.LLEN*2-1:P.LLEN]}, SelSpillM, LSUWriteDataSpillM);
logic [P.LLEN*2/8-1:0] ByteMaskShiftedM; logic [P.LLEN*2/8-1:0] ByteMaskShiftedM;
assign ByteMaskShiftedM = {{{P.LLEN/8}{1'b0}}, ByteMaskM} << (MisalignedM ? ByteMaskM : '0); // *** merge with subword byte mask assign ByteMaskShiftedM = {ByteMaskExtendedM, ByteMaskM};
mux2 #(2*P.LLEN/8) bytemaskspillmux(ByteMaskShiftedM, {{{P.LLEN/8}{1'b0}}, ByteMaskShiftedM[P.LLEN*2/8-1:P.LLEN/8]}, SelSpillM, ByteMaskSpillM); mux2 #(2*P.LLEN/8) bytemaskspillmux(ByteMaskShiftedM, {{{P.LLEN/8}{1'b0}}, ByteMaskExtendedM}, SelSpillM, ByteMaskSpillM);
endmodule endmodule

9
src/lsu/lsu.sv
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@ -134,6 +134,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic [P.LLEN-1:0] LittleEndianWriteDataM; // Ending-swapped write data logic [P.LLEN-1:0] LittleEndianWriteDataM; // Ending-swapped write data
logic [P.LLEN-1:0] LSUWriteDataM; // Final write data logic [P.LLEN-1:0] LSUWriteDataM; // Final write data
logic [(P.LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write logic [(P.LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write
logic [(P.LLEN-1)/8:0] ByteMaskExtendedM; // Selects which bytes within a word to write
logic DTLBMissM; // DTLB miss causes HPTW walk logic DTLBMissM; // DTLB miss causes HPTW walk
logic DTLBWriteM; // Writes PTE and PageType to DTLB logic DTLBWriteM; // Writes PTE and PageType to DTLB
@ -155,7 +156,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M,
.MemRWM, .CacheableM, .MemRWM, .CacheableM,
.DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM, .DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM,
.ByteMaskM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM, .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM,
.IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM); .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM);
assign IEUAdrExtM = {2'b00, IEUAdrSpillM}; assign IEUAdrExtM = {2'b00, IEUAdrSpillM};
assign IEUAdrExtE = {2'b00, IEUAdrSpillE}; assign IEUAdrExtE = {2'b00, IEUAdrSpillE};
@ -261,7 +262,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
// Add support for cboz // Add support for cboz
dtim #(P) dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM), dtim #(P) dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
.DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM), .DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM),
.ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM[P.LLEN/8-1:0])); .ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM));
end else begin end else begin
end end
if (P.BUS_SUPPORTED) begin : bus if (P.BUS_SUPPORTED) begin : bus
@ -337,7 +338,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
ahbinterface #(P.XLEN, 1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), ahbinterface #(P.XLEN, 1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
.HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM[P.XLEN/8-1:0]), .WriteData(LSUWriteDataM[P.XLEN-1:0]), .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
.Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
// Mux between the 2 sources of read data, 0: Bus, 1: DTIM // Mux between the 2 sources of read data, 0: Bus, 1: DTIM
@ -379,7 +380,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM); subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
// Compute byte masks // Compute byte masks
swbytemask #(P.LLEN) swbytemask(.Size(LSUFunct3M), .Adr(PAdrM[$clog2(P.LLEN/8)-1:0]), .ByteMask(ByteMaskM)); swbytemask #(P.LLEN, P.ZICCLSM_SUPPORTED) swbytemask(.Size(LSUFunct3M), .Adr(PAdrM[$clog2(P.LLEN/8)-1:0]), .ByteMask(ByteMaskM), .ByteMaskExtended(ByteMaskExtendedM));
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// MW Pipeline Register // MW Pipeline Register

16
src/lsu/swbytemask.sv
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@ -27,13 +27,21 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module swbytemask #(parameter WORDLEN)( module swbytemask #(parameter WORDLEN, EXTEND = 0)(
input logic [2:0] Size, input logic [2:0] Size,
input logic [$clog2(WORDLEN/8)-1:0] Adr, input logic [$clog2(WORDLEN/8)-1:0] Adr,
output logic [WORDLEN/8-1:0] ByteMask output logic [WORDLEN/8-1:0] ByteMask,
output logic [WORDLEN/8-1:0] ByteMaskExtended
); );
if(EXTEND) begin
assign ByteMask = ((2**(2**Size))-1) << Adr; // merge with align. logic [WORDLEN*2/8-1:0] ExtendedByteMask;
assign ExtendedByteMask = ((2**(2**Size))-1) << Adr;
assign ByteMask = ExtendedByteMask[WORDLEN/8-1:0];
assign ByteMaskExtended = ExtendedByteMask[WORDLEN*2/8-1:WORDLEN/8];
end else begin
assign ByteMask = ((2**(2**Size))-1) << Adr;
assign ByteMaskExtended = '0;
end
/* Equivalent to the following /* Equivalent to the following