diff --git a/sim/wave.do b/sim/wave.do index 8717f667d..7c8eae184 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -256,7 +256,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-c add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SelWay add wave -noupdate -expand -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/IEUAdrE add wave -noupdate -expand -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay @@ -265,7 +264,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay @@ -294,7 +293,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelData} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} @@ -316,7 +314,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelData} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} @@ -426,7 +423,6 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group typ add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv index 4d6330215..f4b12d4af 100644 --- a/src/lsu/amoalu.sv +++ b/src/lsu/amoalu.sv @@ -37,22 +37,38 @@ module amoalu import cvw::*; #(parameter cvw_t P) ( ); logic [P.XLEN-1:0] a, b, y; + logic sngd, eq, lt, eq32, lt32, w64; + + // Share hardware among the four amomin/amomax comparators + assign sngd = ~LSUFunct7M[5]; // Funct7[5] = 0 for signed amomin/max + assign w64 = (LSUFunct3M[1:0] == 2'b10); // operate on bottom 32 bits + assign sngd32 = sngd & (P.XLEN == 32 | w64); + + comparator #(32) cmp32(a[31:0], b[31:0], sngd32, {eq32, lt32}); + if (P.XLEN == 32) begin + assign lt = lt32; + end else begin + logic equpper, ltupper, lt64; + + comparator #(32) cmpupper(a[63:32], b[63:32], sngd, {equpper, ltupper}); + + assign lt64 = ltupper | equpper & lt32; + assign lt = w64 ? lt32 : lt64; + end - // *** see how synthesis generates this and optimize more structurally if necessary to share hardware - // a single carry chain should be shared for + and the four min/max // and the same mux can be used to select b for swap. always_comb case (LSUFunct7M[6:2]) - 5'b00001: y = b; // amoswap - 5'b00000: y = a + b; // amoadd - 5'b00100: y = a ^ b; // amoxor - 5'b01100: y = a & b; // amoand - 5'b01000: y = a | b; // amoor - 5'b10000: y = ($signed(a) < $signed(b)) ? a : b; // amomin - 5'b10100: y = ($signed(a) >= $signed(b)) ? a : b; // amomax - 5'b11000: y = ($unsigned(a) < $unsigned(b)) ? a : b; // amominu - 5'b11100: y = ($unsigned(a) >= $unsigned(b)) ? a : b; // amomaxu - default: y = 'x; // undefined; *** could change to b for efficiency + 5'b00001: y = b; // amoswap + 5'b00000: y = a + b; // amoadd + 5'b00100: y = a ^ b; // amoxor + 5'b01100: y = a & b; // amoand + 5'b01000: y = a | b; // amoor + 5'b10000: y = lt ? a : b; // amomin + 5'b10100: y = lt ? b : a; // amomax + 5'b11000: y = lt ? a : b; // amominu + 5'b11100: y = lt ? b : a; // amomaxu + default: y = 'x; // undefined; *** could change to b for efficiency endcase // sign extend if necessary