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Moved generate for lrsc to lsu.

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This commit is contained in:
Ross Thompson 2021-12-28 14:17:18 -06:00
parent 73af458eb5
commit f09b10a393
2 changed files with 27 additions and 27 deletions
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7
wally-pipelined/src/lsu/lrsc.sv
View File

@ -38,8 +38,6 @@ module lrsc
output logic SquashSCW output logic SquashSCW
); );
// Handle atomic load reserved / store conditional // Handle atomic load reserved / store conditional
generate
if (`A_SUPPORTED) begin // atomic instructions supported
logic [`PA_BITS-1:2] ReservationPAdrW; logic [`PA_BITS-1:2] ReservationPAdrW;
logic ReservationValidM, ReservationValidW; logic ReservationValidM, ReservationValidW;
logic lrM, scM, WriteAdrMatchM; logic lrM, scM, WriteAdrMatchM;
@ -58,9 +56,4 @@ module lrsc
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW); flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW);
end else begin // Atomic operations not supported
assign SquashSCW = 0;
assign DCRWM = LsuRWM;
end
endgenerate
endmodule endmodule

7
wally-pipelined/src/lsu/lsu.sv
View File

@ -258,9 +258,16 @@ module lsu
// Move generate from lrsc to outside this module. // Move generate from lrsc to outside this module.
generate
if (`A_SUPPORTED) begin
assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM, lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM,
.SquashSCW, .DCRWM); .SquashSCW, .DCRWM);
end else begin
assign SquashSCW = 0;
assign DCRWM = LsuRWM;
end
endgenerate
// Specify which type of page fault is occurring // Specify which type of page fault is occurring
// *** `MEM_VIRTMEM // *** `MEM_VIRTMEM