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https://github.com/openhwgroup/cvw
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Moved generate for lrsc to lsu.
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@ -38,8 +38,6 @@ module lrsc
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output logic SquashSCW
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output logic SquashSCW
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);
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);
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// Handle atomic load reserved / store conditional
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// Handle atomic load reserved / store conditional
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generate
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if (`A_SUPPORTED) begin // atomic instructions supported
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logic [`PA_BITS-1:2] ReservationPAdrW;
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logic [`PA_BITS-1:2] ReservationPAdrW;
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logic ReservationValidM, ReservationValidW;
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logic ReservationValidM, ReservationValidW;
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logic lrM, scM, WriteAdrMatchM;
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logic lrM, scM, WriteAdrMatchM;
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@ -58,9 +56,4 @@ module lrsc
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flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
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flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
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flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
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flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
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flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW);
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flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW);
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end else begin // Atomic operations not supported
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assign SquashSCW = 0;
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assign DCRWM = LsuRWM;
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end
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endgenerate
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endmodule
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endmodule
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@ -258,9 +258,16 @@ module lsu
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// Move generate from lrsc to outside this module.
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// Move generate from lrsc to outside this module.
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generate
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if (`A_SUPPORTED) begin
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assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
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assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
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lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM,
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lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM,
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.SquashSCW, .DCRWM);
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.SquashSCW, .DCRWM);
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end else begin
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assign SquashSCW = 0;
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assign DCRWM = LsuRWM;
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end
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endgenerate
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// Specify which type of page fault is occurring
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// Specify which type of page fault is occurring
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// *** `MEM_VIRTMEM
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// *** `MEM_VIRTMEM
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