From f07d4b34811bcaf59cc27107a6e6a004dff494ed Mon Sep 17 00:00:00 2001 From: cturek Date: Fri, 16 Sep 2022 02:15:48 +0000 Subject: [PATCH] Fixed j1 to align with new C reg --- pipelined/src/fpu/fdivsqrtiter.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/pipelined/src/fpu/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrtiter.sv index d76fdb981..9c792d9d4 100644 --- a/pipelined/src/fpu/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrtiter.sv @@ -125,7 +125,8 @@ module fdivsqrtiter( .C(C[i]), .S(S[i]), .SM(SM[i]), .CNext(C[i+1]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i])); end else begin: stage logic j1; - assign j1 = (i == 0 & C[0][`DIVb-2] & ~C[0][`DIVb-3]); + assign j1 = (i == 0 & ~C[0][`DIVb-1]); +// assign j1 = (i == 0 & C[0][`DIVb-2] & ~C[0][`DIVb-3]); fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, .j1, .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]), .C(C[i]), .S(S[i]), .SM(SM[i]), .CNext(C[i+1]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i]));