Removed more generate statements

pipelined/src/cache/cache.sv

@@ -143,7 +143,6 @@ module cache #(parameter integer LINELEN,
 					  .WayHit, .VictimDirtyWay, .VictimTagWay,
 					  .InvalidateAll(InvalidateCacheM));
 
-  generate
   if(NUMWAYS > 1) begin:vict
     cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
     cachereplacementpolicy(.clk, .reset,
@@ -155,7 +154,6 @@ module cache #(parameter integer LINELEN,
   end else begin:vict
     assign VictimWay = 1'b1; // one hot.
   end
-  endgenerate
 
   assign CacheHit = | WayHit;
   assign VictimDirty = | VictimDirtyWay;
@@ -172,33 +170,23 @@ module cache #(parameter integer LINELEN,
   // easily build a variable input mux.
   // *** consider using a limited range shift to do this final muxing.
   genvar index;
-  generate
+	if(DCACHE == 1) begin: readdata
-	if(DCACHE == 1) begin
     for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
 		  assign ReadDataLineSets[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)];
     end
 	  // variable input mux
 	  assign ReadDataWord = ReadDataLineSets[LsuPAdrM[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]];
-
+	end else begin: readdata
-	end else begin
 	  logic [31:0] 				  ReadLineSetsF [LINELEN/16-1:0];
 	  logic [31:0] 				  FinalInstrRawF;
-	  for(index = 0; index < LINELEN / 16 - 1; index++) begin:readlinesetsmux
+	  for(index = 0; index < LINELEN / 16 - 1; index++) 
 		  assign ReadLineSetsF[index] = ReadDataLineM[((index+1)*16)+16-1 : (index*16)];
-	  end
 	  assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadDataLineM[LINELEN-1:LINELEN-16]};
-
 	  assign FinalInstrRawF = ReadLineSetsF[LsuPAdrM[$clog2(LINELEN / 32) + 1 : 1]];
-	  if (`XLEN == 64) begin
+	  if (`XLEN == 64) assign ReadDataWord = {32'b0, FinalInstrRawF};		
-		assign ReadDataWord = {32'b0, FinalInstrRawF};		
+	  else             assign ReadDataWord = FinalInstrRawF;				
-	  end else begin
-	  assign ReadDataWord = FinalInstrRawF;				
 	end
 
-	end
-  endgenerate
-
-
   // Write Path CPU (IEU) side
 
   onehotdecoder #(LOGWPL)

pipelined/src/uncore/gpio.sv

@@ -61,10 +61,10 @@ module gpio (
   // account for subword read/write circuitry
   // -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
   //    (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported")
-  if (`XLEN == 64) begin:gpio
+  if (`XLEN == 64) begin
     assign Din =       entryd[2] ? HWDATA[63:32] : HWDATA[31:0];
     assign HREADGPIO = entryd[2] ? {Dout,32'b0}  : {32'b0,Dout};
-  end else begin:gpio // 32-bit
+  end else begin // 32-bit
     assign Din = HWDATA[31:0];
     assign HREADGPIO = Dout;
   end
@@ -140,12 +140,9 @@ module gpio (
   end
 
   // chip i/o
-  generate
+  // connect OUT to IN for loopback testing
-    if (`GPIO_LOOPBACK_TEST) // connect OUT to IN for loopback testing
+  if (`GPIO_LOOPBACK_TEST) assign input0d = GPIOPinsOut & input_en & output_en;
-      assign input0d = GPIOPinsOut & input_en & output_en;
+  else                     assign input0d = GPIOPinsIn  & input_en;
-    else
-      assign input0d = GPIOPinsIn & input_en;
-  endgenerate
   flop #(32) sync1(HCLK,input0d,input1d);
   flop #(32) sync2(HCLK,input1d,input2d);
   flop #(32) sync3(HCLK,input2d,input3d);

pipelined/src/uncore/plic.sv

@@ -77,23 +77,13 @@ module plic (
 
   // account for subword read/write circuitry
   // -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
-  generate
+    if (`XLEN == 64) begin
-    if (`XLEN == 64) begin:plic
+    assign Din       = entryd[2] ? HWDATA[63:32] : HWDATA[31:0];
-      always_comb
+    assign HREADPLIC = entryd[2] ? {Dout,32'b0}  : {32'b0,Dout};
-        if (entryd[2]) begin
+  end else begin // 32-bit
-          Din = HWDATA[63:32];
+    assign Din       = HWDATA[31:0];
-          HREADPLIC = {Dout,32'b0};
+    assign HREADPLIC = Dout;
-        end else begin
-          Din = HWDATA[31:0];
-          HREADPLIC = {32'b0,Dout};
   end
-    end else begin:plic // 32-bit
-      always_comb begin
-        Din = HWDATA[31:0];
-        HREADPLIC = Dout;
-      end
-    end
-  endgenerate
 
   // ==================
   // Register Interface
@@ -165,14 +155,11 @@ module plic (
 
   // pending array - indexed by priority_lvl x source_ID
   genvar i, j;
-  generate
   for (j=1; j<=7; j++) begin: pending
     for (i=1; i<=N; i=i+1) begin: pendingbit
-        // *** make sure that this synthesizes into N decoders, not 7*N 3-bit equality comparators (right?)
       assign pendingArray[j][i] = (intPriority[i]==j) & intEn[i] & intPending[i];
     end
   end
-  endgenerate
   // pending array, except grouped by priority
   assign pendingPGrouped[7:1] = {|pendingArray[7],
                                  |pendingArray[6],
@@ -200,8 +187,7 @@ module plic (
                                     | ({N{pendingMaxP[2]}} & pendingArray[2])
                                     | ({N{pendingMaxP[1]}} & pendingArray[1]);
   // find the lowest ID amongst active interrupts at the highest priority
-  int k;
+  int k; // *** rewrite as priority encoder
-  // *** verify that this synthesizes to a reasonable priority encoder and that k doesn't actually exist in hardware
   always_comb begin
     intClaim = 6'b0;
     for(k=N; k>0; k=k-1) begin