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Renamed Flush to FlushStage in the cache.

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This commit is contained in:
Ross Thompson 2022-11-14 14:11:05 -06:00
parent 1bf838fa6b
commit f03d5d3ac8
5 changed files with 15 additions and 15 deletions
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8
pipelined/src/cache/cache.sv vendored
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@ -34,7 +34,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
input logic clk,
input logic reset,
// cpu side
input logic Flush,
input logic FlushStage,
input logic CPUBusy,
input logic [1:0] CacheRW,
input logic [1:0] CacheAtomic,
@ -126,11 +126,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN)
CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .LineWriteData, .LineByteMask,
.SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Flush,
.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .FlushStage,
.Invalidate(InvalidateCache));
if(NUMWAYS > 1) begin:vict
cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(
.clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn(LRUWriteEn & ~Flush));
.clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage));
end else assign VictimWay = 1'b1; // one hot.
assign CacheHit = | HitWay;
assign VictimDirty = | VictimDirtyWay;
@ -207,7 +207,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
// Cache FSM
/////////////////////////////////////////////////////////////////////////////////////////////
cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
.Flush, .CacheRW, .CacheAtomic, .CPUBusy,
.FlushStage, .CacheRW, .CacheAtomic, .CPUBusy,
.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr,
.ClearValid, .ClearDirty, .SetDirty,

4
pipelined/src/cache/cachefsm.sv vendored
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@ -34,7 +34,7 @@ module cachefsm
(input logic clk,
input logic reset,
// inputs from IEU
input logic Flush,
input logic FlushStage,
input logic [1:0] CacheRW,
input logic [1:0] CacheAtomic,
input logic FlushCache,
@ -111,7 +111,7 @@ module cachefsm
flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay));
always_ff @(posedge clk)
if (reset | Flush) CurrState <= #1 STATE_READY;
if (reset | FlushStage) CurrState <= #1 STATE_READY;
else CurrState <= #1 NextState;
always_comb begin

14
pipelined/src/cache/cacheway.sv vendored
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@ -48,7 +48,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
input logic VictimWay,
input logic FlushWay,
input logic Invalidate,
input logic Flush,
input logic FlushStage,
// input logic [(`XLEN-1)/8:0] ByteMask,
input logic [LINELEN/8-1:0] LineByteMask,
@ -87,7 +87,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce,
.addr(RAdr), .dout(ReadTag), .bwe('1),
.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidWay & ~Flush));
.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidWay & ~FlushStage));
// AND portion of distributed tag multiplexer
mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
@ -110,7 +110,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce, .addr(RAdr),
.dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
.din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
.we(SelectedWriteWordEn & ~Flush), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
.we(SelectedWriteWordEn & ~FlushStage), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
end
// AND portion of distributed read multiplexers
@ -124,8 +124,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
always_ff @(posedge clk) begin // Valid bit array,
if (reset | Invalidate) ValidBits <= #1 '0;
if(ce) begin Valid <= #1 ValidBits[RAdr];
if (SetValidWay & ~Flush) ValidBits[RAdr] <= #1 1'b1;
else if (ClearValidWay & ~Flush) ValidBits[RAdr] <= #1 1'b0;
if (SetValidWay & ~FlushStage) ValidBits[RAdr] <= #1 1'b1;
else if (ClearValidWay & ~FlushStage) ValidBits[RAdr] <= #1 1'b0;
end
end
@ -139,8 +139,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
if(ce) begin
Dirty <= #1 DirtyBits[RAdr];
if (SetDirtyWay & ~Flush) DirtyBits[RAdr] <= #1 1'b1;
else if (ClearDirtyWay & ~Flush) DirtyBits[RAdr] <= #1 1'b0;
if (SetDirtyWay & ~FlushStage) DirtyBits[RAdr] <= #1 1'b1;
else if (ClearDirtyWay & ~FlushStage) DirtyBits[RAdr] <= #1 1'b0;
end
end
end else assign Dirty = 1'b0;

2
pipelined/src/ifu/ifu.sv
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@ -221,7 +221,7 @@ module ifu (
cache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
icache(.clk, .reset, .Flush(FlushW), .CPUBusy,
icache(.clk, .reset, .FlushStage(FlushW), .CPUBusy,
.FetchBuffer, .CacheBusAck(ICacheBusAck),
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
.CacheBusRW,

2
pipelined/src/lsu/lsu.sv
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@ -248,7 +248,7 @@ module lsu (
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache(
.clk, .reset, .CPUBusy, .SelBusBeat, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
.clk, .reset, .CPUBusy, .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
.FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM),
.ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
.CacheWriteData(LSUWriteDataM), .SelHPTW,