diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 5217067eb..afed3dd23 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -7,3 +7,4 @@ lsu/lsu.sv: logic PAdrM lsu/lsu.sv: logic ReadDataM lsu/lsu.sv: logic WriteDataM lsu/lsu.sv: logic MemRWM +privileged/csrc.sv: logic HPMCOUNTER_REGW diff --git a/fpga/constraints/small-debug.xdc b/fpga/constraints/small-debug.xdc index 44151c6bf..10d64c126 100644 --- a/fpga/constraints/small-debug.xdc +++ b/fpga/constraints/small-debug.xdc @@ -19,7 +19,7 @@ connect_debug_port u_ila_0/clk [get_nets CPUCLK] set_property port_width 32 [get_debug_ports u_ila_0/probe0] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {RvviAxiRdata[0]} {RvviAxiRdata[1]} {RvviAxiRdata[2]} {RvviAxiRdata[3]} {RvviAxiRdata[4]} {RvviAxiRdata[5]} {RvviAxiRdata[6]} {RvviAxiRdata[7]} {RvviAxiRdata[8]} {RvviAxiRdata[9]} {RvviAxiRdata[10]} {RvviAxiRdata[11]} {RvviAxiRdata[12]} {RvviAxiRdata[13]} {RvviAxiRdata[14]} {RvviAxiRdata[15]} {RvviAxiRdata[16]} {RvviAxiRdata[17]} {RvviAxiRdata[18]} {RvviAxiRdata[19]} {RvviAxiRdata[20]} {RvviAxiRdata[21]} {RvviAxiRdata[22]} {RvviAxiRdata[23]} {RvviAxiRdata[24]} {RvviAxiRdata[25]} {RvviAxiRdata[26]} {RvviAxiRdata[27]} {RvviAxiRdata[28]} {RvviAxiRdata[29]} {RvviAxiRdata[30]} {RvviAxiRdata[31]} ]] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][0]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][1]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][2]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][3]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][4]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][5]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][6]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][7]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][8]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][9]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][10]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][11]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][12]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][13]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][14]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][15]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][16]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][17]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][18]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][19]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][20]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][21]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][22]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][23]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][24]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][25]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][26]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][27]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][28]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][29]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][30]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][31]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe1] @@ -91,26 +91,6 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe13] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] connect_debug_port u_ila_0/probe13 [get_nets [list {RvviAxiRvalid}]] -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe14] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list {triggergen/IlaTriggerOneCycle}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe15] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {triggergen/TriggerReset}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe16] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list {triggergen/TriggerEn}]] - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe17] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list {triggergen/TriggerCount[0]} {triggergen/TriggerCount[1]} {triggergen/TriggerCount[2]} {triggergen/TriggerCount[3]}]] - # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] diff --git a/src/rvvi/triggergen.sv b/src/rvvi/triggergen.sv index 1b7e3ef4f..0a4269024 100644 --- a/src/rvvi/triggergen.sv +++ b/src/rvvi/triggergen.sv @@ -45,7 +45,7 @@ module triggergen import cvw::*; ( logic [3:0] RvviAxiRstrbDelay; logic RvviAxiRvalidDelay; logic Match, Overflow, Mismatch, Threshold; -(* mark_debug = "true" *) logic IlaTriggerOneCycle; + logic IlaTriggerOneCycle; assign mem[0] = 32'h1111_6843; // dst mac [31:0] assign mem[1] = 32'h1654_4502; // src mac [15:0], dst mac [47:32] @@ -99,11 +99,12 @@ module triggergen import cvw::*; ( end -----/\----- EXCLUDED -----/\----- */ -(* mark_debug = "true" *) logic [3:0] TriggerCount; -(* mark_debug = "true" *) logic TriggerReset, TriggerEn; - counter #(4) triggercounter(clk, reset | TriggerReset, TriggerEn, TriggerCount); - assign TriggerReset = TriggerCount == 4'd10; - assign TriggerEn = IlaTriggerOneCycle | (TriggerCount != 4'd0 & TriggerCount < 4'd10); - assign IlaTrigger = TriggerEn; + // this is a bit hacky, but it works! + logic [3:0] TriggerCount; + logic TriggerReset, TriggerEn; + counter #(4) triggercounter(clk, reset | TriggerReset, TriggerEn, TriggerCount); + assign TriggerReset = TriggerCount == 4'd10; + assign TriggerEn = IlaTriggerOneCycle | (TriggerCount != 4'd0 & TriggerCount < 4'd10); + assign IlaTrigger = TriggerEn; endmodule