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fix ICache indenting

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This commit is contained in:
Ben Bracker 2021-07-03 11:11:07 -05:00
parent 1fa4abf7b6
commit eff5a1b90f
2 changed files with 123 additions and 127 deletions
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10
wally-pipelined/regression/wave-dos/linux-waves.do
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@ -122,11 +122,11 @@ add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UEPC_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG01_REGW #add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG01_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG23_REGW #add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG23_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW #add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW #add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW #add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW
add wave -divider add wave -divider
add wave -hex -r /testbench/* add wave -hex -r /testbench/*

240
wally-pipelined/src/cache/ICacheCntrl.sv vendored
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@ -213,179 +213,175 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
ICacheStallF = 1'b1; ICacheStallF = 1'b1;
case (CurrState) case (CurrState)
STATE_READY: begin STATE_READY: begin
PCMux = 2'b00; PCMux = 2'b00;
ICacheReadEn = 1'b1; ICacheReadEn = 1'b1;
if (ITLBMissF) begin if (ITLBMissF) begin
NextState = STATE_TLB_MISS; NextState = STATE_TLB_MISS;
end else if (hit & ~spill) begin end else if (hit & ~spill) begin
SavePC = 1'b1; SavePC = 1'b1;
ICacheStallF = 1'b0; ICacheStallF = 1'b0;
NextState = STATE_READY;
end else if (hit & spill) begin
spillSave = 1'b1;
PCMux = 2'b10;
NextState = STATE_HIT_SPILL;
end else if (~hit & ~spill) begin
CntReset = 1'b1;
NextState = STATE_MISS_FETCH_WDV;
end else if (~hit & spill) begin
CntReset = 1'b1;
PCMux = 2'b01;
NextState = STATE_MISS_SPILL_FETCH_WDV;
end else begin
NextState = STATE_READY; NextState = STATE_READY;
end end else if (hit & spill) begin
spillSave = 1'b1;
PCMux = 2'b10;
NextState = STATE_HIT_SPILL;
end else if (~hit & ~spill) begin
CntReset = 1'b1;
NextState = STATE_MISS_FETCH_WDV;
end else if (~hit & spill) begin
CntReset = 1'b1;
PCMux = 2'b01;
NextState = STATE_MISS_SPILL_FETCH_WDV;
end else begin
NextState = STATE_READY;
end
end end
// branch 1, hit spill and 2, miss spill hit // branch 1, hit spill and 2, miss spill hit
STATE_HIT_SPILL: begin STATE_HIT_SPILL: begin
PCMux = 2'b10; PCMux = 2'b10;
UnalignedSelect = 1'b1; UnalignedSelect = 1'b1;
ICacheReadEn = 1'b1; ICacheReadEn = 1'b1;
if (hit) begin if (hit) begin
NextState = STATE_HIT_SPILL_FINAL; NextState = STATE_HIT_SPILL_FINAL;
end else begin end else begin
CntReset = 1'b1; CntReset = 1'b1;
NextState = STATE_HIT_SPILL_MISS_FETCH_WDV; NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
end end
end end
STATE_HIT_SPILL_MISS_FETCH_WDV: begin STATE_HIT_SPILL_MISS_FETCH_WDV: begin
PCMux = 2'b10; PCMux = 2'b10;
//InstrReadF = 1'b1; //InstrReadF = 1'b1;
PreCntEn = 1'b1; PreCntEn = 1'b1;
if (FetchCountFlag & InstrAckF) begin if (FetchCountFlag & InstrAckF) begin
NextState = STATE_HIT_SPILL_MISS_FETCH_DONE; NextState = STATE_HIT_SPILL_MISS_FETCH_DONE;
end else begin end else begin
NextState = STATE_HIT_SPILL_MISS_FETCH_WDV; NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
end end
end end
STATE_HIT_SPILL_MISS_FETCH_DONE: begin STATE_HIT_SPILL_MISS_FETCH_DONE: begin
PCMux = 2'b10; PCMux = 2'b10;
ICacheMemWriteEnable = 1'b1; ICacheMemWriteEnable = 1'b1;
NextState = STATE_HIT_SPILL_MERGE; NextState = STATE_HIT_SPILL_MERGE;
end end
STATE_HIT_SPILL_MERGE: begin STATE_HIT_SPILL_MERGE: begin
PCMux = 2'b10; PCMux = 2'b10;
UnalignedSelect = 1'b1; UnalignedSelect = 1'b1;
ICacheReadEn = 1'b1; ICacheReadEn = 1'b1;
NextState = STATE_HIT_SPILL_FINAL; NextState = STATE_HIT_SPILL_FINAL;
end end
STATE_HIT_SPILL_FINAL: begin STATE_HIT_SPILL_FINAL: begin
ICacheReadEn = 1'b1; ICacheReadEn = 1'b1;
PCMux = 2'b00; PCMux = 2'b00;
UnalignedSelect = 1'b1; UnalignedSelect = 1'b1;
SavePC = 1'b1; SavePC = 1'b1;
NextState = STATE_READY; NextState = STATE_READY;
ICacheStallF = 1'b0; ICacheStallF = 1'b0;
end end
// branch 3 miss no spill // branch 3 miss no spill
STATE_MISS_FETCH_WDV: begin STATE_MISS_FETCH_WDV: begin
PCMux = 2'b01; PCMux = 2'b01;
//InstrReadF = 1'b1; //InstrReadF = 1'b1;
PreCntEn = 1'b1; PreCntEn = 1'b1;
if (FetchCountFlag & InstrAckF) begin if (FetchCountFlag & InstrAckF) begin
NextState = STATE_MISS_FETCH_DONE; NextState = STATE_MISS_FETCH_DONE;
end else begin end else begin
NextState = STATE_MISS_FETCH_WDV; NextState = STATE_MISS_FETCH_WDV;
end end
end end
STATE_MISS_FETCH_DONE: begin STATE_MISS_FETCH_DONE: begin
PCMux = 2'b01; PCMux = 2'b01;
ICacheMemWriteEnable = 1'b1; ICacheMemWriteEnable = 1'b1;
NextState = STATE_MISS_READ; NextState = STATE_MISS_READ;
end end
STATE_MISS_READ: begin STATE_MISS_READ: begin
PCMux = 2'b01; PCMux = 2'b01;
ICacheReadEn = 1'b1; ICacheReadEn = 1'b1;
NextState = STATE_READY; NextState = STATE_READY;
end end
// branch 4 miss spill hit, and 5 miss spill miss // branch 4 miss spill hit, and 5 miss spill miss
STATE_MISS_SPILL_FETCH_WDV: begin STATE_MISS_SPILL_FETCH_WDV: begin
PCMux = 2'b01; PCMux = 2'b01;
PreCntEn = 1'b1; PreCntEn = 1'b1;
//InstrReadF = 1'b1; //InstrReadF = 1'b1;
if (FetchCountFlag & InstrAckF) begin if (FetchCountFlag & InstrAckF) begin
NextState = STATE_MISS_SPILL_FETCH_DONE; NextState = STATE_MISS_SPILL_FETCH_DONE;
end else begin end else begin
NextState = STATE_MISS_SPILL_FETCH_WDV; NextState = STATE_MISS_SPILL_FETCH_WDV;
end end
end end
STATE_MISS_SPILL_FETCH_DONE: begin STATE_MISS_SPILL_FETCH_DONE: begin
PCMux = 2'b01; PCMux = 2'b01;
ICacheMemWriteEnable = 1'b1; ICacheMemWriteEnable = 1'b1;
NextState = STATE_MISS_SPILL_READ1; NextState = STATE_MISS_SPILL_READ1;
end end
STATE_MISS_SPILL_READ1: begin // always be a hit as we just wrote that cache block. STATE_MISS_SPILL_READ1: begin // always be a hit as we just wrote that cache block.
PCMux = 2'b01; // there is a 1 cycle delay after setting the address before the date arrives. PCMux = 2'b01; // there is a 1 cycle delay after setting the address before the date arrives.
ICacheReadEn = 1'b1; ICacheReadEn = 1'b1;
NextState = STATE_MISS_SPILL_2; NextState = STATE_MISS_SPILL_2;
end end
STATE_MISS_SPILL_2: begin STATE_MISS_SPILL_2: begin
PCMux = 2'b10; PCMux = 2'b10;
UnalignedSelect = 1'b1; UnalignedSelect = 1'b1;
spillSave = 1'b1; /// *** Could pipeline these to make it clearer in the fsm. spillSave = 1'b1; /// *** Could pipeline these to make it clearer in the fsm.
ICacheReadEn = 1'b1; ICacheReadEn = 1'b1;
NextState = STATE_MISS_SPILL_2_START; NextState = STATE_MISS_SPILL_2_START;
end end
STATE_MISS_SPILL_2_START: begin STATE_MISS_SPILL_2_START: begin
if (~hit) begin if (~hit) begin
CntReset = 1'b1; CntReset = 1'b1;
NextState = STATE_MISS_SPILL_MISS_FETCH_WDV; NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
end else begin end else begin
NextState = STATE_READY; NextState = STATE_READY;
ICacheReadEn = 1'b1; ICacheReadEn = 1'b1;
PCMux = 2'b00; PCMux = 2'b00;
UnalignedSelect = 1'b1; UnalignedSelect = 1'b1;
SavePC = 1'b1; SavePC = 1'b1;
ICacheStallF = 1'b0; ICacheStallF = 1'b0;
end end
end end
STATE_MISS_SPILL_MISS_FETCH_WDV: begin STATE_MISS_SPILL_MISS_FETCH_WDV: begin
PCMux = 2'b10; PCMux = 2'b10;
PreCntEn = 1'b1; PreCntEn = 1'b1;
//InstrReadF = 1'b1; //InstrReadF = 1'b1;
if (FetchCountFlag & InstrAckF) begin if (FetchCountFlag & InstrAckF) begin
NextState = STATE_MISS_SPILL_MISS_FETCH_DONE; NextState = STATE_MISS_SPILL_MISS_FETCH_DONE;
end else begin end else begin
NextState = STATE_MISS_SPILL_MISS_FETCH_WDV; NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
end end
end end
STATE_MISS_SPILL_MISS_FETCH_DONE: begin STATE_MISS_SPILL_MISS_FETCH_DONE: begin
PCMux = 2'b10; PCMux = 2'b10;
ICacheMemWriteEnable = 1'b1; ICacheMemWriteEnable = 1'b1;
NextState = STATE_MISS_SPILL_MERGE; NextState = STATE_MISS_SPILL_MERGE;
end end
STATE_MISS_SPILL_MERGE: begin STATE_MISS_SPILL_MERGE: begin
PCMux = 2'b10; PCMux = 2'b10;
UnalignedSelect = 1'b1; UnalignedSelect = 1'b1;
ICacheReadEn = 1'b1; ICacheReadEn = 1'b1;
NextState = STATE_MISS_SPILL_FINAL; NextState = STATE_MISS_SPILL_FINAL;
end end
STATE_MISS_SPILL_FINAL: begin STATE_MISS_SPILL_FINAL: begin
ICacheReadEn = 1'b1; ICacheReadEn = 1'b1;
PCMux = 2'b00; PCMux = 2'b00;
UnalignedSelect = 1'b1; UnalignedSelect = 1'b1;
SavePC = 1'b1; SavePC = 1'b1;
ICacheStallF = 1'b0; ICacheStallF = 1'b0;
NextState = STATE_READY; NextState = STATE_READY;
end end
STATE_TLB_MISS: begin STATE_TLB_MISS: begin
if (ITLBWriteF | WalkerInstrPageFaultF) begin if (ITLBWriteF | WalkerInstrPageFaultF) begin
NextState = STATE_TLB_MISS_DONE; NextState = STATE_TLB_MISS_DONE;
end else begin end else begin
NextState = STATE_TLB_MISS; NextState = STATE_TLB_MISS;
end end
end end
STATE_TLB_MISS_DONE : begin STATE_TLB_MISS_DONE : begin
NextState = STATE_READY; NextState = STATE_READY;
end end
default: begin default: begin
PCMux = 2'b01; PCMux = 2'b01;
NextState = STATE_READY; NextState = STATE_READY;
end end
// *** add in error handling and invalidate/evict // *** add in error handling and invalidate/evict
endcase endcase