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fix ICache indenting

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This commit is contained in:
Ben Bracker 2021-07-03 11:11:07 -05:00
parent 1fa4abf7b6
commit eff5a1b90f
2 changed files with 123 additions and 127 deletions
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10
wally-pipelined/regression/wave-dos/linux-waves.do
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@ -122,11 +122,11 @@ add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UEPC_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG01_REGW #add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG01_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG23_REGW #add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG23_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW #add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW #add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW #add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW
add wave -divider add wave -divider
add wave -hex -r /testbench/* add wave -hex -r /testbench/*

4
wally-pipelined/src/cache/ICacheCntrl.sv vendored
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@ -213,7 +213,6 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
ICacheStallF = 1'b1; ICacheStallF = 1'b1;
case (CurrState) case (CurrState)
STATE_READY: begin STATE_READY: begin
PCMux = 2'b00; PCMux = 2'b00;
ICacheReadEn = 1'b1; ICacheReadEn = 1'b1;
@ -238,7 +237,6 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
NextState = STATE_READY; NextState = STATE_READY;
end end
end end
// branch 1, hit spill and 2, miss spill hit // branch 1, hit spill and 2, miss spill hit
STATE_HIT_SPILL: begin STATE_HIT_SPILL: begin
PCMux = 2'b10; PCMux = 2'b10;
@ -280,7 +278,6 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
NextState = STATE_READY; NextState = STATE_READY;
ICacheStallF = 1'b0; ICacheStallF = 1'b0;
end end
// branch 3 miss no spill // branch 3 miss no spill
STATE_MISS_FETCH_WDV: begin STATE_MISS_FETCH_WDV: begin
PCMux = 2'b01; PCMux = 2'b01;
@ -302,7 +299,6 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
ICacheReadEn = 1'b1; ICacheReadEn = 1'b1;
NextState = STATE_READY; NextState = STATE_READY;
end end
// branch 4 miss spill hit, and 5 miss spill miss // branch 4 miss spill hit, and 5 miss spill miss
STATE_MISS_SPILL_FETCH_WDV: begin STATE_MISS_SPILL_FETCH_WDV: begin
PCMux = 2'b01; PCMux = 2'b01;