From efa9f0986470d2df997772e173c620e302579ec8 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 22 Mar 2023 10:31:21 -0700 Subject: [PATCH] updated header comments to indicate chapter 15 --- src/ieu/bmu/bitreverse.sv | 2 +- src/ieu/bmu/bmuctrl.sv | 4 +--- src/ieu/bmu/byte.sv | 2 +- src/ieu/bmu/clmul.sv | 2 +- src/ieu/bmu/cnt.sv | 2 +- src/ieu/bmu/ext.sv | 2 +- src/ieu/bmu/popcnt.sv | 2 ++ src/ieu/bmu/zbb.sv | 2 +- src/ieu/bmu/zbc.sv | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 86024a348..e2afb0c95 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -8,7 +8,7 @@ // // Purpose: Bit reverse submodule // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index b09bec11b..ae401ef88 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -7,7 +7,7 @@ // // Purpose: Top level bit manipulation instruction decoder // -// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // @@ -165,8 +165,6 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor 17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 - //17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) - // BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) 17'b0010011_0010100_101: if (`ZBB_SUPPORTED & Rs2D[4:0] == 5'b00111) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b 17'b0110011_0000101_110: if (`ZBB_SUPPORTED) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 8cf3f0e56..db7a3b45c 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -7,7 +7,7 @@ // // Purpose: RISCV bitmanip byte-wise operation unit // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index b96f3af60..904c64238 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -7,7 +7,7 @@ // // Purpose: Carry-Less multiplication unit // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 296e6d383..13ff1e15f 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -8,7 +8,7 @@ // // Purpose: Count Instruction Submodule // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 250616b58..12e690436 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -8,7 +8,7 @@ // // Purpose: Sign/Zero Extension Submodule // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index f7e18b151..77c4b6158 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -6,6 +6,8 @@ // // Purpose: Population Count // +// Documentation: RISC-V System on Chip Design Chapter 15 +// // A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 89ae7beb4..1e2c8437b 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -8,7 +8,7 @@ // // Purpose: RISC-V ZBB top level unit // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 5ed04bc02..05e05d38f 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V ZBC top-level unit // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. //