Separate fcov and lockstep

bin/wsim

@@ -27,7 +27,7 @@ def parseArgs():
     parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
     parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
     parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
-    parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true")
+    parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif", action="store_true")
     parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
     parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
     parser.add_argument("--define", "-d", help="Optional define macros passed to simulator", default="")
@@ -101,15 +101,15 @@ def prepSim(args, ElfFile):
         flagsList.append("--ccov")
     if args.fcov:
         flagsList.append("--fcov")
-        defineList.extend(["+define+INCLUDE_TRACE2COV", "+define+IDV_INCLUDE_TRACE2COV", "+define+COVER_BASE_RV32I"]) # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but does not affect tests
+        defineList.extend(["+define+ENABLE_RVVI_TRACE", "+define+INCLUDE_TRACE2COV", "+define+IDV_INCLUDE_TRACE2COV", "+define+COVER_BASE_RV32I"]) # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but does not affect tests
         argsList.extend(["+TRACE2COV_ENABLE=1", "+IDV_TRACE2COV=1"])
     if args.gui:
         flagsList.append("--gui")
     if args.lockstep or args.lockstepverbose:
         flagsList.append("--lockstep")
-    if args.lockstep or args.lockstepverbose or args.fcov:
+    if args.lockstep or args.lockstepverbose:
         prefix = lockstepSetup(args)
-        defineList.append("+define+USE_IMPERAS_DV")
+        defineList.extend(["+define+USE_IMPERAS_DV", "+define+ENABLE_RVVI_TRACE"])
     if args.config == "breker": # Requires a license for the breker tool. See tests/breker/README.md for details
         ElfFileNoExtension = os.path.splitext(ElfFile)[0]
         flagsList.append("--breker")
@@ -154,7 +154,6 @@ def runQuesta(args, flags, prefix):
         args.params = fr'--params \"{args.params}\"'
     if args.define:
         args.define = fr'--define \"{args.define}\"'
-    # fcov implies lockstep
     cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {args.define} {flags}"
     cmd = f'cd $WALLY/sim/questa; {prefix} vsim {"-c" if not args.gui else ""} -do "{cmd}"'
     print(f"Running Questa with command: {cmd}")

sim/questa/wally.do

@@ -111,15 +111,22 @@ if {[lcheck lst "--ccov"]} {
 
 # if --fcov found set flag and remove from list
 if {[lcheck lst "--fcov"]} {
+    set IMPERAS_HOME $::env(IMPERAS_HOME)
     set FunctCoverage 1
+    # ImpProprietary is needed for trace2cov for now
     set FCvlog "+incdir+${FCRVVI}/unpriv \
                 +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/rv32_priv \
                 +incdir+${FCRVVI}/common +incdir+${FCRVVI} \
-                +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source"
+                +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \
+                +incdir+${IMPERAS_HOME}/ImpPublic/include/host \
+                +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \
+                -f ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvvi.f \
+                -f ${IMPERAS_HOME}/ImpProprietary/source/host/idv/idv.f"
+    set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model "
 }
 
-# if --lockstep or --fcov found set flag and remove from list
-if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} {
+# if --lockstep found set flag and remove from list
+if {[lcheck lst "--lockstep"]} {
     set IMPERAS_HOME $::env(IMPERAS_HOME)
     set lockstep 1
     set lockstepvlog "+incdir+${IMPERAS_HOME}/ImpPublic/include/host \

testbench/testbench.sv

@@ -731,17 +731,22 @@ module testbench;
     end
 end
 
+// RVVI trace for functional coverage and lockstep
+`ifdef ENABLE_RVVI_TRACE
+  rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi();
+  wallyTracer #(P) wallyTracer(rvvi);
+`endif
+
+// Functional coverage
+`ifdef INCLUDE_TRACE2COV
+  trace2cov idv_trace2cov(rvvi); // needed for fcov as of now
+`endif
+
   ////////////////////////////////////////////////////////////////////////////////
   // ImperasDV Co-simulator hooks
   ////////////////////////////////////////////////////////////////////////////////
 `ifdef USE_IMPERAS_DV
 
-  rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi();
-  wallyTracer #(P) wallyTracer(rvvi);
-
-  trace2log idv_trace2log(rvvi);
-  trace2cov idv_trace2cov(rvvi);
-
   // enabling of comparison types
   trace2api #(.CMP_PC      (1),
               .CMP_INS     (1),
@@ -751,6 +756,8 @@ end
               .CMP_CSR     (1)
               ) idv_trace2api(rvvi);
 
+  // trace2log idv_trace2log(rvvi); // currently not used
+
   string filename;
   initial begin
     // imperasDV requires the elffile be defined at the begining of the simulation.