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hptw: factored Misaligned

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This commit is contained in:
David Harris 2021-07-17 11:31:16 -04:00
parent e3b26b7b23
commit ef83a44c4d
1 changed files with 13 additions and 21 deletions
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34
wally-pipelined/src/mmu/pagetablewalker.sv
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@ -78,15 +78,8 @@ module pagetablewalker
logic [`PPN_BITS-1:0] CurrentPPN; logic [`PPN_BITS-1:0] CurrentPPN;
logic [`SVMODE_BITS-1:0] SvMode; logic [`SVMODE_BITS-1:0] SvMode;
logic MemStore; logic MemStore;
logic Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid;
// PTE Control Bits logic ValidPTE, ADPageFault, MegapageMisaligned, TerapageMisaligned, GigapageMisaligned, BadMegapage, LeafPTE;
logic Dirty, Accessed, Global, User,
Executable, Writable, Readable, Valid;
// PTE descriptions
logic ValidPTE, ADPageFault, MegapageMisaligned, BadMegapage, LeafPTE;
// Outputs of walker
//logic [`XLEN-1:0] PageTableEntry;
logic StartWalk; logic StartWalk;
logic EndWalk; logic EndWalk;
@ -203,15 +196,24 @@ module pagetablewalker
default: TranslationPAdr = 0; // cause seg fault if this is improperly used default: TranslationPAdr = 0; // cause seg fault if this is improperly used
endcase endcase
end end
if (`XLEN == 32) begin
assign TerapageMisaligned = 0; // not applicable
assign GigapageMisaligned = 0; // not applicable
assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
end else begin
assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0
assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0
assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0
end
// generate // generate
if (`XLEN == 32) begin if (`XLEN == 32) begin
// A megapage is a Level 1 leaf page. This page must have zero PPN[0]. // A megapage is a Level 1 leaf page. This page must have zero PPN[0].
assign MegapageMisaligned = |(CurrentPPN[9:0]);
// State transition logic // State transition logic
always_comb begin always_comb begin
å case (WalkerState) case (WalkerState)
IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE; IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE;
else NextWalkerState = IDLE; else NextWalkerState = IDLE;
LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV; LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV;
@ -226,7 +228,6 @@ module pagetablewalker
LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV; LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV;
LEVEL0_WDV: if (HPTWStall) NextWalkerState = LEVEL0_WDV; LEVEL0_WDV: if (HPTWStall) NextWalkerState = LEVEL0_WDV;
else NextWalkerState = LEVEL0; else NextWalkerState = LEVEL0;
end
LEVEL0: if (ValidPTE & LeafPTE & ~ADPageFault) NextWalkerState = LEAF; LEVEL0: if (ValidPTE & LeafPTE & ~ADPageFault) NextWalkerState = LEAF;
else NextWalkerState = FAULT; else NextWalkerState = FAULT;
LEAF: NextWalkerState = IDLE; LEAF: NextWalkerState = IDLE;
@ -242,15 +243,6 @@ module pagetablewalker
assign HPTWPAdrE = TranslationPAdr[31:0]; assign HPTWPAdrE = TranslationPAdr[31:0];
end else begin end else begin
logic TerapageMisaligned, GigapageMisaligned;
// A terapage is a level 3 leaf page. This page must have zero PPN[2],
// zero PPN[1], and zero PPN[0]
assign TerapageMisaligned = |(CurrentPPN[26:0]);
// A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and
// zero PPN[0]
assign GigapageMisaligned = |(CurrentPPN[17:0]);
// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
assign MegapageMisaligned = |(CurrentPPN[8:0]);
always_comb begin always_comb begin
case (WalkerState) case (WalkerState)