improved implementation, simulation running w/ few passes

src/hazard/hazard.sv

@@ -30,7 +30,7 @@
 module hazard import cvw::*;  #(parameter cvw_t P) ( 
   input  logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,
   input  logic  StructuralStallD,
-  input  logic  LSUStallM, IFUStallF,
+  input  logic  LSUStallM, IFUStallF, FetchBufferStallF,
   input  logic  FPUStallD, ExternalStall,
   input  logic  DivBusyE, FDivBusyE,
   input  logic  wfiM, IntPendingM,
@@ -82,7 +82,7 @@ module hazard import cvw::*;  #(parameter cvw_t P) (
   //  The IFU and LSU stall the entire pipeline on a cache miss, bus access, or other long operation.  
   //    The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions
   //    A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation
-  assign StallFCause = 1'b0;
+  assign StallFCause = FetchBufferStallF;
   assign StallDCause = (StructuralStallD | FPUStallD) & ~FlushDCause;
   assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; 
   assign StallMCause = WFIStallM & ~FlushMCause;

src/ifu/fetchbuffer.sv

@@ -28,10 +28,10 @@
 
 module fetchbuffer import cvw::*; #(parameter cvw_t P) (
 	input  logic        clk, reset,
-	input  logic        StallD, flush,
+	input  logic        StallD, FlushD,
 	input  logic [31:0] writeData,
 	output logic [31:0] readData,
-	output logic        StallF
+	output logic        FetchBufferStallF
 );
   localparam [31:0] nop = 32'h00000013;
   logic      [31:0] readf0, readf1, readf2, readMuxed;
@@ -40,19 +40,19 @@ module fetchbuffer import cvw::*; #(parameter cvw_t P) (
 
   assign empty  = |(readPtr & writePtr); // Bitwise and the read&write ptr, and or the bits of the result together
   assign full   = |({writePtr[1:0], writePtr[2]} & readPtr); // Same as above but left rotate writePtr to "add 1"
-  assign StallF = full;
+  assign FetchBufferStallF = full;
 
   // will go in a generate block once this is parameterized
-  flopenr f0 (.clk, .reset(reset | flush), .en(writePtr[0]), .d(writeData), .q(readf0)); 
+  flopenr #(32) f0 (.clk, .reset(reset | FlushD), .en(writePtr[0]), .d(writeData), .q(readf0)); 
-  flopenr f1 (.clk, .reset(reset | flush), .en(writePtr[1]), .d(writeData), .q(readf1));
+  flopenr #(32) f1 (.clk, .reset(reset | FlushD), .en(writePtr[1]), .d(writeData), .q(readf1));
-  flopenr f2 (.clk, .reset(reset | flush), .en(writePtr[2]), .d(writeData), .q(readf2));
+  flopenr #(32) f2 (.clk, .reset(reset | FlushD), .en(writePtr[2]), .d(writeData), .q(readf2));
 
   always_comb begin : readMuxes
     // Mux read data from the three registers
     case (readPtr)
       3'b001:  readMuxed = readf0;
       3'b010:  readMuxed = readf1;
-      3'b001:  readMuxed = readf2;
+      3'b100:  readMuxed = readf2;
       default: readMuxed = nop; // just in case?
     endcase
     // issue nop when appropriate

src/ifu/ifu.sv

@@ -95,7 +95,9 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   input  var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],// PMP address from privileged unit
   output logic                 InstrAccessFaultF,                        // Instruction access fault 
   output logic                 ICacheAccess,                             // Report I$ read to performance counters
-  output logic                 ICacheMiss                                // Report I$ miss to performance counters
+  output logic                 ICacheMiss,                               // Report I$ miss to performance counters
+  // Fetch Buffer
+  output logic FetchBufferStallF                                         // Report Fetch Buffer Stall to Hazard Unit
 );
 
   localparam [31:0]            nop = 32'h00000013;                       // instruction for NOP
@@ -303,7 +305,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   
   // flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
   // TODO: Test this?!?!?!
-  fetchbuffer #(P) fetchbuff(.clk, .reset, .StallD, .flush(FlushD), .writeData(PostSpillInstrRawF), .readData(InstrRawD), .StallF); // Figure out what TODO with StallF
+  fetchbuffer #(P) fetchbuff(.clk, .reset, .StallD, .FlushD, .writeData(PostSpillInstrRawF), .readData(InstrRawD), .FetchBufferStallF); // Figure out what TODO with StallF
 
   ////////////////////////////////////////////////////////////////////////////////////////////////
   // PCNextF logic

src/wally/wallypipelinedcore.sv

@@ -170,6 +170,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   logic                          DCacheStallM, ICacheStallF;
   logic                          wfiM, IntPendingM;
 
+  // Fetch Buffer Stall
+  logic                          FetchBufferStallF;
+
   // instruction fetch unit: PC, branch prediction, instruction cache
   ifu #(P) ifu(.clk, .reset,
     .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
@@ -177,7 +180,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
     .BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF,
     // Fetch
     .HRDATA, .PCSpillF, .IFUHADDR, 
-    .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
+    .IFUStallF, .FetchBufferStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
     .ICacheAccess, .ICacheMiss,
     // Execute
     .PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPWrongE,  .BPWrongM, 
@@ -274,7 +277,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   hazard #(P) hzu(
     .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
     .StructuralStallD,
-    .LSUStallM, .IFUStallF,
+    .LSUStallM, .IFUStallF, .FetchBufferStallF,
     .FPUStallD, .ExternalStall,
     .DivBusyE, .FDivBusyE,
     .wfiM, .IntPendingM,