From ee1e09a6a240c9930cfea2c4e01d0dc4026a9f0a Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 23 Aug 2024 17:18:47 -0700 Subject: [PATCH] VCU108 now boot linux at 50MHz! --- fpga/constraints/constraints-vcu108.xdc | 8 ++-- fpga/src/fpgaTop.sv | 4 +- linux/devicetree/wally-artya7.dts | 8 ++-- linux/devicetree/wally-vcu108.dts | 58 ++++++++++++++++++------- 4 files changed, 53 insertions(+), 25 deletions(-) diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc index b30b4273c..638cfb2a5 100644 --- a/fpga/constraints/constraints-vcu108.xdc +++ b/fpga/constraints/constraints-vcu108.xdc @@ -11,8 +11,8 @@ create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] set_property PACKAGE_PIN E34 [get_ports {GPI[0]}] set_property PACKAGE_PIN M22 [get_ports {GPI[1]}] set_property PACKAGE_PIN AW27 [get_ports {GPI[2]}] -set_property PACKAGE_PIN A10 [get_ports {GPI[3]}] -set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}] +#set_property PACKAGE_PIN A10 [get_ports {GPI[3]}] +#set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[2]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}] @@ -59,7 +59,7 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_port set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset] set_max_delay -from [get_ports reset] 15.000 set_false_path -from [get_ports reset] -set_property PACKAGE_PIN E34 [get_ports {reset}] +set_property PACKAGE_PIN A10 [get_ports {reset}] set_property IOSTANDARD LVCMOS12 [get_ports {reset}] @@ -104,7 +104,7 @@ set_property PACKAGE_PIN AW12 [get_ports SDCCD] set_property IOSTANDARD LVCMOS18 [get_ports SDCCD] set_property PULLTYPE PULLUP [get_ports SDCCD] set_property PACKAGE_PIN BC16 [get_ports SDCWP] -set_property IOSTANDARD LVCMO18 [get_ports SDCWP] +set_property IOSTANDARD LVCMOS18 [get_ports SDCWP] set_property PULLTYPE PULLUP [get_ports SDCWP] #set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv index 058a2ea52..9ae282966 100644 --- a/fpga/src/fpgaTop.sv +++ b/fpga/src/fpgaTop.sv @@ -34,7 +34,7 @@ module fpgaTop input reset, input south_rst, - input [3:0] GPI, + input [2:0] GPI, output [4:0] GPO, input UARTSin, @@ -183,7 +183,7 @@ module fpgaTop logic CLK208; - assign GPIOIN = {25'b0, SDCCD, SDCWP, 1'b0, GPI}; + assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI}; assign GPO = GPIOOUT[4:0]; assign ahblite_resetn = peripheral_aresetn; assign cpu_reset = bus_struct_reset; diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts index 99b8ff00d..5b0580695 100644 --- a/linux/devicetree/wally-artya7.dts +++ b/linux/devicetree/wally-artya7.dts @@ -21,8 +21,8 @@ cpus { #address-cells = <0x01>; #size-cells = <0x00>; - clock-frequency = <0x1312D00>; - timebase-frequency = <0x1312D00>; + clock-frequency = <0x17D7840>; + timebase-frequency = <0x17D7840>; cpu@0 { phandle = <0x01>; @@ -54,7 +54,7 @@ refclk: refclk { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <0x1312D00>; + clock-frequency = <0x17D7840>; clock-output-names = "xtal"; }; @@ -73,7 +73,7 @@ uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; - clock-frequency = <0x1312D00>; + clock-frequency = <0x17D7840>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; diff --git a/linux/devicetree/wally-vcu108.dts b/linux/devicetree/wally-vcu108.dts index 8c9182c6c..ef3694066 100644 --- a/linux/devicetree/wally-vcu108.dts +++ b/linux/devicetree/wally-vcu108.dts @@ -9,7 +9,7 @@ chosen { linux,initrd-end = <0x85c43a00>; linux,initrd-start = <0x84200000>; - bootargs = "console=ttyS0,115200 root=/dev/vda ro"; + bootargs = "root=/dev/vda ro console=ttyS0,115200 loglevel=7"; stdout-path = "/soc/uart@10000000"; }; @@ -21,8 +21,8 @@ cpus { #address-cells = <0x01>; #size-cells = <0x00>; - clock-frequency = <0x14FB180>; - timebase-frequency = <0x14FB180>; + clock-frequency = <0x2FAF080>; + timebase-frequency = <0x2FAF080>; cpu@0 { phandle = <0x01>; @@ -31,6 +31,9 @@ status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcsu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm"; + riscv,cbom-block-size = <64>; mmu-type = "riscv,sv48"; interrupt-controller { @@ -48,10 +51,29 @@ compatible = "simple-bus"; ranges; + refclk: refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x2FAF080>; + clock-output-names = "xtal"; + }; + + gpio0: gpio@10060000 { + compatible = "sifive,gpio0"; + interrupt-parent = <0x03>; + interrupts = <3>; + reg = <0x00 0x10060000 0x00 0x1000>; + reg-names = "control"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; - clock-frequency = <0x14FB180>; + clock-frequency = <0x2FAF080>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; @@ -67,18 +89,24 @@ #address-cells = <0x00>; }; - mmc@13000 { - interrupts = <0x14>; - compatible = "riscv,axi-sd-card-1.0"; - reg = <0x00 0x13000 0x00 0x7F>; - fifo-depth = <256>; - bus-width = <4>; + spi@13000 { + compatible = "sifive,spi0"; interrupt-parent = <0x03>; - clock = <0x14FB180>; - max-frequency = <0xA7D8C0>; - cap-sd-highspeed; - cap-mmc-highspeed; - no-sdio; + interrupts = <0x14>; + reg = <0x0 0x13000 0x0 0x1000>; + reg-names = "control"; + clocks = <&refclk>; + + #address-cells = <1>; + #size-cells = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <5000000>; + voltage-ranges = <3300 3300>; + disable-wp; + // gpios = <&gpio0 6 1>; + }; }; clint@2000000 {