mmu cleanup

pipelined/src/mmu/adrdec.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Address decoder
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/mmu/adrdecs.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: All the address decoders for peripherals
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/mmu/hptw.sv

@@ -8,8 +8,9 @@
 //            adding support for terapage encoding, and for setting the HPTWAdr using the new level,
 //            adding the internal SvMode signal
 //
-// Purpose: Page Table Walker
-//          Part of the Memory Management Unit (MMU)
+// Purpose: Hardware Page Table Walker
+//
+// Documentation: RISC-V System on Chip Design Chapter 8
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 //
@@ -94,9 +95,7 @@ module hptw (
   logic                       DTLBMissOrDAFaultM;
   logic [`PA_BITS-1:0]        HPTWAdr;
   logic [1:0]                 HPTWRW;
-  logic [2:0]                 HPTWSize; // 32 or 64 bit access.
-                       
-
+  logic [2:0]                 HPTWSize; // 32 or 64 bit access
 	(* mark_debug = "true" *) statetype WalkerState, NextWalkerState, InitialWalkerState;
 
 
@@ -112,7 +111,6 @@ module hptw (
 
 	// Determine which address to translate
 	mux2 #(`XLEN) vadrmux(PCF, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr);
-	//assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF;
 	assign CurrentPPN = PTE[`PPN_BITS+9:10];
 
 	// State flops
@@ -120,7 +118,6 @@ module hptw (
 	assign PRegEn = HPTWRW[1] & ~DCacheStallW | UpdatePTE;
 	flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache
 
-    
 	// Assign PTE descriptors common across all XLEN values
 	// For non-leaf PTEs, D, A, U bits are reserved and ignored.  They do not cause faults while walking the page table
 	assign {PTE_U, Executable, Writable, Readable, Valid} = PTE[4:0];
@@ -130,7 +127,6 @@ module hptw (
 	assign ValidNonLeafPTE = ValidPTE & ~LeafPTE;
 
   if(`HPTW_WRITES_SUPPORTED) begin : hptwwrites
-
     logic                     ReadAccess, WriteAccess;
     logic                     InvalidRead, InvalidWrite;
     logic                     UpperBitsUnequalPageFault; 
@@ -190,7 +186,6 @@ module hptw (
 	assign DTLBWriteM = (WalkerState == LEAF & ~DAPageFault) & DTLBWalk;
 	assign ITLBWriteF = (WalkerState == LEAF & ~DAPageFault) & ~DTLBWalk;
   
-
 	// FSM to track PageType based on the levels of the page table traversed
 	flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
 	always_comb 
@@ -280,7 +275,6 @@ module hptw (
   assign SelHPTW = WalkerState != IDLE;
   assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss);
 
-
   assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF);
   assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM);  
 

pipelined/src/mmu/mmu.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Memory management unit, including TLB, PMA, PMP
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@@ -29,8 +31,10 @@
 module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
   input  logic                clk, reset,
   input  logic [`XLEN-1:0]    SATP_REGW,          // Current value of satp CSR (from privileged unit)
-  input logic                 STATUS_MXR, STATUS_SUM, STATUS_MPRV, // Status bits affecting translation
-  input logic [1:0]           STATUS_MPP,         // previous machine privilege level
+  input  logic                STATUS_MXR,         // Status CSR: make executable page readable
+  input  logic                STATUS_SUM,         // Status CSR: Supervisor access to user memory
+  input  logic                STATUS_MPRV,        // Status CSR: modify machine privilege
+  input  logic [1:0]          STATUS_MPP,         // Status CSR: previous machine privilege level
   input  logic [1:0]          PrivilegeModeW,     // Current privilege level of the processeor
   input  logic                DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses
   input  logic [`XLEN+1:0]    VAdr,               // virtual/physical address from IEU or physical address from HPTW
@@ -103,10 +107,16 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
     .Cacheable, .Idempotent, .SelTIM,
     .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
  
+  if (`PMP_ENTRIES > 0) // instantiate PMP
     pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
       .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
       .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
+  else begin
+    assign PMPInstrAccessFaultF = 0;
+    assign PMPLoadAccessFaultM = 0;
+    assign PMPStoreAmoAccessFaultM = 0;
+  end
 
   // Access faults
   // If TLB miss and translating we want to not have faults from the PMA and PMP checkers.

pipelined/src/mmu/pmachecker.sv

@@ -8,6 +8,8 @@
 //          the memory region accessed.
 //          Can report illegal accesses to the trap unit and cause a fault.
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@@ -31,7 +33,10 @@
 module pmachecker (
   input  logic [`PA_BITS-1:0] PhysicalAddress,
   input  logic [1:0]          Size,
-  input  logic        AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use.
+  input  logic                AtomicAccessM,  // Atomic access
+  input  logic                ExecuteAccessF, // Execute access 
+  input  logic                WriteAccessM,   // Write access 
+  input  logic                ReadAccessM,    // Read access
   output logic                Cacheable, Idempotent, SelTIM,
   output logic                PMAInstrAccessFaultF,
   output logic                PMALoadAccessFaultM,

pipelined/src/mmu/pmpadrdec.sv

@@ -10,6 +10,8 @@
 //          naturally aligned power-of-two region/NAPOT), then selects the
 //          output based on which mode is input.
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@@ -40,6 +42,7 @@ module pmpadrdec (
   output logic                  L, X, W, R
 );
   
+  // define PMP addressing mode codes
   localparam                    TOR   = 2'b01;
   localparam                    NA4   = 2'b10;
   localparam                    NAPOT = 2'b11;
@@ -49,7 +52,6 @@ module pmpadrdec (
   logic [`PA_BITS-1:0]          CurrentAdrFull;
   logic [1:0]                   AdrMode;
 
-
   assign AdrMode = PMPCfg[4:3];
 
   // The two lsb of the physical address don't matter for this checking.

pipelined/src/mmu/pmpchecker.sv

@@ -9,6 +9,8 @@
 //          Can raise an access fault on illegal reads, writes, and instruction
 //          fetches.
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@@ -32,8 +34,7 @@
 module pmpchecker (
   input  logic [`PA_BITS-1:0]      PhysicalAddress,  
   input  logic [1:0]               PrivilegeModeW,
-
-  // *** ModelSim has a switch -svinputport which controls whether input ports
+  // ModelSim has a switch -svinputport which controls whether input ports
   // are nets (wires) or vars by default. The default setting of this switch is
   // `relaxed`, which means that signals are nets if and only if they are
   // scalars or one-dimensional vectors. Since this is a two-dimensional vector,
@@ -48,7 +49,6 @@ module pmpchecker (
   output logic                     PMPStoreAmoAccessFaultM
 );
 
-  if (`PMP_ENTRIES > 0) begin: pmpchecker
   // Bit i is high when the address falls in PMP region i
   logic                    EnforcePMP;
   logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges
@@ -73,9 +73,4 @@ module pmpchecker (
   assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
   assign PMPStoreAmoAccessFaultM  = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;
   assign PMPLoadAccessFaultM      = EnforcePMP & ReadAccessM    & ~|(R & FirstMatch) ;
-  end else begin: pmpchecker  // no checker
-    assign PMPInstrAccessFaultF = 0;
-    assign PMPLoadAccessFaultM = 0;
-    assign PMPStoreAmoAccessFaultM = 0;
-  end
  endmodule

pipelined/src/mmu/tlb.sv

@@ -9,6 +9,8 @@
 // Purpose: Translation lookaside buffer
 //          Cache of virtural-to-physical address translations
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/mmu/tlbcam.sv

@@ -9,6 +9,8 @@
 // Purpose: Stores virtual page numbers with cached translations.
 //          Determines whether a given virtual page number is in the TLB.
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/mmu/tlbcamline.sv

@@ -9,6 +9,8 @@
 // Purpose: CAM line for the translation lookaside buffer (TLB)
 //          Determines whether a virtual page number matches the stored key.
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/mmu/tlbcontrol.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Control signals for TLB
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/mmu/tlblru.sv

@@ -7,6 +7,8 @@
 // Purpose: Implementation of bit pseudo least-recently-used algorithm for
 //          cache evictions. Outputs the index of the next entry to be written.
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/mmu/tlbmixer.sv

@@ -9,6 +9,8 @@
 //          number with segments from the second, based on the page type.
 //          NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type.
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/mmu/tlbram.sv

@@ -8,6 +8,8 @@
 //          Outputs the physical page number and access bits of the current
 //          virtual address on a TLB hit.
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/mmu/tlbramline.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/mmu/vm64check.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Check for good upper address bits in RV64 mode
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University