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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed ShiftEdge and SampleEdge to not always include PhaseOneOffset. Before, it worked in simulation, but not on the FPGA.
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parent
56a6ad3376
commit
eddae8e1a6
@ -243,10 +243,34 @@ module spi_controller (
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SampleEdge <= 0;
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SampleEdge <= 0;
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EndOfFrameDelay <= 0;
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EndOfFrameDelay <= 0;
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end else begin
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end else begin
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ShiftEdge <= ((SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & ~LastBit & Transmitting) & PhaseOneOffset;
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case(SckMode)
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PhaseOneOffset <= PhaseOneOffset == 0 ? Transmitting & SCLKenable : ~EndOfFrameDelay;
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2'b00: begin
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SampleEdge <= (SckMode[1] ^ SckMode[0] ^ ~SPICLK) & SCLKenable & Transmitting & ~DelayIsNext;
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ShiftEdge <= SPICLK & SCLKenable & ~LastBit & Transmitting;
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EndOfFrameDelay <= (SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & LastBit & Transmitting;
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SampleEdge <= ~SPICLK & SCLKenable & Transmitting & ~DelayIsNext;
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EndOfFrameDelay <= SPICLK & SCLKenable & LastBit & Transmitting;
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end
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2'b01: begin
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ShiftEdge <= ~SPICLK & SCLKenable & ~LastBit & Transmitting & PhaseOneOffset;
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SampleEdge <= SPICLK & SCLKenable & Transmitting & ~DelayIsNext;
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EndOfFrameDelay <= ~SPICLK & SCLKenable & LastBit & Transmitting;
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PhaseOneOffset <= (PhaseOneOffset == 0) ? Transmitting & SCLKenable : ~EndOfFrameDelay;
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end
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2'b10: begin
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ShiftEdge <= ~SPICLK & SCLKenable & ~LastBit & Transmitting;
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SampleEdge <= SPICLK & SCLKenable & Transmitting & ~DelayIsNext;
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EndOfFrameDelay <= ~SPICLK & SCLKenable & LastBit & Transmitting;
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end
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2'b11: begin
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ShiftEdge <= SPICLK & SCLKenable & ~LastBit & Transmitting & PhaseOneOffset;
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SampleEdge <= ~SPICLK & SCLKenable & Transmitting & ~DelayIsNext;
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EndOfFrameDelay <= SPICLK & SCLKenable & LastBit & Transmitting;
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PhaseOneOffset <= (PhaseOneOffset == 0) ? Transmitting & SCLKenable : ~EndOfFrameDelay;
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end
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// ShiftEdge <= ((SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & ~LastBit & Transmitting) & PhaseOneOffset;
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// PhaseOneOffset <= PhaseOneOffset == 0 ? Transmitting & SCLKenable : ~EndOfFrameDelay;
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// SampleEdge <= (SckMode[1] ^ SckMode[0] ^ ~SPICLK) & SCLKenable & Transmitting & ~DelayIsNext;
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// EndOfFrameDelay <= (SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & LastBit & Transmitting;
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endcase
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end
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end
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end
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end
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@ -314,8 +338,9 @@ module spi_controller (
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SCKCS: begin // SCKCS case --------------------------------------
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SCKCS: begin // SCKCS case --------------------------------------
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if (EndOfSCKCS) begin
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if (EndOfSCKCS) begin
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if (~ContinueTransmitD) begin
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if (~ContinueTransmitD) begin
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if (CSMode == AUTOMODE) NextState = INACTIVE;
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// if (CSMode == AUTOMODE) NextState = INACTIVE;
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else if (CSMode == HOLDMODE) NextState = HOLD;
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if (CSMode == HOLDMODE) NextState = HOLD;
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else NextState = INACTIVE;
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end else begin
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end else begin
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if (HasINTERCS) NextState = INTERCS;
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if (HasINTERCS) NextState = INTERCS;
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else NextState = TRANSMIT;
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else NextState = TRANSMIT;
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