Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Formating.

Browse Source
This commit is contained in:
Ross Thompson 2023-01-18 16:52:46 -06:00
parent 32589a5efc
commit edc4630742
2 changed files with 34 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
pipelined/src/ebu/ahbcacheinterface.sv
View File

@ -4,11 +4,9 @@
// Written: Ross Thompson ross1728@gmail.com August 29, 2022
// Modified:
//
// Purpose: Cache/Bus data path.
// Bus Side logic
// register the fetch data from the next level of memory.
// This register should be necessary for timing. There is no register in the uncore or
// ahblite controller between the memories and this cache.
// Purpose: Translates cache bus requests and uncached ieu memory requests into AHB transactions.
//
// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//

14
pipelined/src/ebu/buscachefsm.sv
View File

@ -1,10 +1,13 @@
///////////////////////////////////////////
// busfsm.sv
//
// Written: Ross Thompson ross1728@gmail.com December 29, 2021
// Modified:
// Written: Ross Thompson ross1728@gmail.com
// Created: December 29, 2021
// Modified: 18 January 2023
//
// Purpose: Load/Store Unit's interface to BUS for cacheless system
// Purpose: Controller for cache to AHB bus interface
//
// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
@ -28,7 +31,10 @@
`define BURST_EN 1
// HCLK and clk must be the same clock!
module buscachefsm #(parameter integer BeatCountThreshold, AHBWLOGBWPL) (
module buscachefsm #(
parameter integer BeatCountThreshold, // Largest beat index
parameter integer AHBWLOGBWPL // Log2 of BEATSPERLINE
)(
input logic HCLK,
input logic HRESETn,