Formating.

pipelined/src/ebu/ahbcacheinterface.sv

@@ -4,11 +4,9 @@
 // Written: Ross Thompson ross1728@gmail.com August 29, 2022
 // Modified: 
 //
-// Purpose: Cache/Bus data path.
+// Purpose: Translates cache bus requests and uncached ieu memory requests into AHB transactions.
-// Bus Side logic
+//
-// register the fetch data from the next level of memory.
+// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8)
-// This register should be necessary for timing.  There is no register in the uncore or
-// ahblite controller between the memories and this cache.
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 

pipelined/src/ebu/buscachefsm.sv

@@ -1,10 +1,13 @@
 ///////////////////////////////////////////
 // busfsm.sv
 //
-// Written: Ross Thompson ross1728@gmail.com December 29, 2021
+// Written: Ross Thompson ross1728@gmail.com 
-// Modified: 
+// Created: December 29, 2021
+// Modified: 18 January 2023 
 //
-// Purpose: Load/Store Unit's interface to BUS for cacheless system
+// Purpose: Controller for cache to AHB bus interface
+// 
+// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -28,7 +31,10 @@
 `define BURST_EN 1
 
 // HCLK and clk must be the same clock!
-module buscachefsm #(parameter integer BeatCountThreshold, AHBWLOGBWPL) (
+module buscachefsm #(
+  parameter integer BeatCountThreshold,              // Largest beat index
+  parameter integer AHBWLOGBWPL                      // Log2 of BEATSPERLINE
+)(
   input  logic              HCLK,
   input  logic              HRESETn,