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				https://github.com/openhwgroup/cvw
				synced 2025-02-11 06:05:49 +00:00 
			
		
		
		
	Fixed unsupported riscof YAML string; preparing for Verilator -G testcase
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				@ -1,6 +1,8 @@
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#!/bin/bash
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# simulate with Verilator
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# verilator --timescale "1ns/1ns" --timing --binary -GTEST="arch64i" --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
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export PATH=$PATH:/usr/local/bin/
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verilator=`which verilator`
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@ -9,7 +11,7 @@ basepath=$(dirname $0)/..
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for config in  rv64gc; do
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    echo "$config simulating..."
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    # not working: -GTEST="arch64i"
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    if !($verilator --timescale "1ns/1ns" --timing --binary "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv   $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
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    if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="arch64i" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv   $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
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        echo "Exiting after $config lint due to errors or warnings"
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        exit 1
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    fi
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@ -35,7 +35,7 @@ module testbench;
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  /* verilator lint_off WIDTHTRUNC */
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  /* verilator lint_off WIDTHEXPAND */
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  parameter DEBUG=0;
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  parameter TEST="none";
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  parameter string TEST="arch64m";
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  parameter PrintHPMCounters=0;
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  parameter BPRED_LOGGER=0;
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  parameter I_CACHE_ADDR_LOGGER=0;
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@ -1,7 +1,8 @@
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hart_ids: [0]
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hart0:
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#  ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zbb_Zbc_Zbs # Zkbs_Zcb
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  ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zbb_Zbc_Zbs # Zkbs_Zcb
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#  ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zbb_Zbc_Zbs # Zkbs_Zcb
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  ISA: RV64IMAFDCSUZicsr_Zifencei_Zbb_Zbc_Zbs # Zkbs_Zcb
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  physical_addr_sz: 56
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  User_Spec_Version: '2.3'
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  supported_xlen: [64]
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