Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-03 02:05:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fixed unsupported riscof YAML string; preparing for Verilator -G testcase

Browse Source
This commit is contained in:
David Harris 2024-01-05 20:06:21 -08:00
parent f0dd913a77
commit ed623f1a71
3 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
sim/verilate
View File

@ -1,6 +1,8 @@
#!/bin/bash #!/bin/bash
# simulate with Verilator # simulate with Verilator
# verilator --timescale "1ns/1ns" --timing --binary -GTEST="arch64i" --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
export PATH=$PATH:/usr/local/bin/ export PATH=$PATH:/usr/local/bin/
verilator=`which verilator` verilator=`which verilator`
@ -9,7 +11,7 @@ basepath=$(dirname $0)/..
for config in rv64gc; do for config in rv64gc; do
echo "$config simulating..." echo "$config simulating..."
# not working: -GTEST="arch64i" # not working: -GTEST="arch64i"
if !($verilator --timescale "1ns/1ns" --timing --binary "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="arch64i" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
echo "Exiting after $config lint due to errors or warnings" echo "Exiting after $config lint due to errors or warnings"
exit 1 exit 1
fi fi

2
testbench/testbench.sv
View File

@ -35,7 +35,7 @@ module testbench;
/* verilator lint_off WIDTHTRUNC */ /* verilator lint_off WIDTHTRUNC */
/* verilator lint_off WIDTHEXPAND */ /* verilator lint_off WIDTHEXPAND */
parameter DEBUG=0; parameter DEBUG=0;
parameter TEST="none"; parameter string TEST="arch64m";
parameter PrintHPMCounters=0; parameter PrintHPMCounters=0;
parameter BPRED_LOGGER=0; parameter BPRED_LOGGER=0;
parameter I_CACHE_ADDR_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0;

3
tests/riscof/spike/spike_rv64gc_isa.yaml
View File

@ -1,7 +1,8 @@
hart_ids: [0] hart_ids: [0]
hart0: hart0:
# ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zbb_Zbc_Zbs # Zkbs_Zcb # ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zbb_Zbc_Zbs # Zkbs_Zcb
ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zbb_Zbc_Zbs # Zkbs_Zcb # ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zbb_Zbc_Zbs # Zkbs_Zcb
ISA: RV64IMAFDCSUZicsr_Zifencei_Zbb_Zbc_Zbs # Zkbs_Zcb
physical_addr_sz: 56 physical_addr_sz: 56
User_Spec_Version: '2.3' User_Spec_Version: '2.3'
supported_xlen: [64] supported_xlen: [64]