Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally

Browse Source
This commit is contained in:
cturek 2022-12-14 15:13:44 +00:00
commit ed59736a4b
13 changed files with 39 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
pipelined/src/cache/cache.sv vendored
View File

@ -35,7 +35,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
input logic reset, input logic reset,
// cpu side // cpu side
input logic FlushStage, input logic FlushStage,
input logic CPUBusy, input logic Stall,
input logic [1:0] CacheRW, input logic [1:0] CacheRW,
input logic [1:0] CacheAtomic, input logic [1:0] CacheAtomic,
input logic FlushCache, input logic FlushCache,
@ -194,7 +194,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
// Cache FSM // Cache FSM
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
.FlushStage, .CacheRW, .CacheAtomic, .CPUBusy, .FlushStage, .CacheRW, .CacheAtomic, .Stall,
.CacheHit, .LineDirty, .CacheStall, .CacheCommitted, .CacheHit, .LineDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr, .CacheMiss, .CacheAccess, .SelAdr,
.ClearValid, .ClearDirty, .SetDirty, .ClearValid, .ClearDirty, .SetDirty,

6
pipelined/src/cache/cachefsm.sv vendored
View File

@ -40,7 +40,7 @@ module cachefsm
input logic FlushCache, input logic FlushCache,
input logic InvalidateCache, input logic InvalidateCache,
// hazard inputs // hazard inputs
input logic CPUBusy, input logic Stall,
// Bus inputs // Bus inputs
input logic CacheBusAck, input logic CacheBusAck,
// dcache internals // dcache internals
@ -130,7 +130,7 @@ module cachefsm
//STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY; //STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY;
STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_DELAY; STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_DELAY;
//else NextState = STATE_READY; //else NextState = STATE_READY;
STATE_MISS_READ_DELAY: if(CPUBusy) NextState = STATE_MISS_READ_DELAY; STATE_MISS_READ_DELAY: if(Stall) NextState = STATE_MISS_READ_DELAY;
else NextState = STATE_READY; else NextState = STATE_READY;
STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_FETCH_WDV; STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_FETCH_WDV;
else NextState = STATE_MISS_EVICT_DIRTY; else NextState = STATE_MISS_EVICT_DIRTY;
@ -201,6 +201,6 @@ module cachefsm
resetDelay; resetDelay;
assign SelFetchBuffer = CurrState == STATE_MISS_WRITE_CACHE_LINE | CurrState == STATE_MISS_READ_DELAY; assign SelFetchBuffer = CurrState == STATE_MISS_WRITE_CACHE_LINE | CurrState == STATE_MISS_READ_DELAY;
assign ce = (CurrState == STATE_READY & ~CPUBusy | CacheStall) | (CurrState != STATE_READY) | reset; assign ce = (CurrState == STATE_READY & ~Stall | CacheStall) | (CurrState != STATE_READY) | reset;
endmodule // cachefsm endmodule // cachefsm

4
pipelined/src/ebu/ahbcacheinterface.sv
View File

@ -64,7 +64,7 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
input logic Flush, input logic Flush,
input logic [`PA_BITS-1:0] PAdr, input logic [`PA_BITS-1:0] PAdr,
input logic [1:0] BusRW, input logic [1:0] BusRW,
input logic CPUBusy, input logic Stall,
input logic [2:0] Funct3, input logic [2:0] Funct3,
output logic SelBusBeat, output logic SelBusBeat,
output logic BusStall, output logic BusStall,
@ -114,7 +114,7 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
.HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
.CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
.HREADY, .HTRANS, .HWRITE, .HBURST); .HREADY, .HTRANS, .HWRITE, .HBURST);
endmodule endmodule

4
pipelined/src/ebu/ahbinterface.sv
View File

@ -51,7 +51,7 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter
input logic [1:0] BusRW, input logic [1:0] BusRW,
input logic [`XLEN/8-1:0] ByteMask, input logic [`XLEN/8-1:0] ByteMask,
input logic [`XLEN-1:0] WriteData, input logic [`XLEN-1:0] WriteData,
input logic CPUBusy, input logic Stall,
output logic BusStall, output logic BusStall,
output logic BusCommitted, output logic BusCommitted,
output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer); output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer);
@ -73,6 +73,6 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter
end end
busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW, busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
.BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY, .BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY,
.HTRANS, .HWRITE); .HTRANS, .HWRITE);
endmodule endmodule

4
pipelined/src/ebu/buscachefsm.sv
View File

@ -40,7 +40,7 @@ module buscachefsm #(parameter integer BeatCountThreshold,
// IEU interface // IEU interface
input logic Flush, input logic Flush,
input logic [1:0] BusRW, input logic [1:0] BusRW,
input logic CPUBusy, input logic Stall,
output logic BusCommitted, output logic BusCommitted,
output logic BusStall, output logic BusStall,
output logic CaptureEn, output logic CaptureEn,
@ -89,7 +89,7 @@ module buscachefsm #(parameter integer BeatCountThreshold,
else NextState = ADR_PHASE; else NextState = ADR_PHASE;
DATA_PHASE: if(HREADY) NextState = MEM3; DATA_PHASE: if(HREADY) NextState = MEM3;
else NextState = DATA_PHASE; else NextState = DATA_PHASE;
MEM3: if(CPUBusy) NextState = MEM3; MEM3: if(Stall) NextState = MEM3;
else NextState = ADR_PHASE; else NextState = ADR_PHASE;
CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK;
else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;

4
pipelined/src/ebu/busfsm.sv
View File

@ -38,7 +38,7 @@ module busfsm
// IEU interface // IEU interface
input logic Flush, input logic Flush,
input logic [1:0] BusRW, input logic [1:0] BusRW,
input logic CPUBusy, input logic Stall,
output logic BusCommitted, output logic BusCommitted,
output logic BusStall, output logic BusStall,
output logic CaptureEn, output logic CaptureEn,
@ -65,7 +65,7 @@ module busfsm
else NextState = ADR_PHASE; else NextState = ADR_PHASE;
DATA_PHASE: if(HREADY) NextState = MEM3; DATA_PHASE: if(HREADY) NextState = MEM3;
else NextState = DATA_PHASE; else NextState = DATA_PHASE;
MEM3: if(CPUBusy) NextState = MEM3; MEM3: if(Stall) NextState = MEM3;
else NextState = ADR_PHASE; else NextState = ADR_PHASE;
default: NextState = ADR_PHASE; default: NextState = ADR_PHASE;
endcase endcase

3
pipelined/src/hazard/hazard.sv
View File

@ -41,7 +41,7 @@ module hazard(
(* mark_debug = "true" *) input logic wfiM, IntPendingM, (* mark_debug = "true" *) input logic wfiM, IntPendingM,
// Stall & flush outputs // Stall & flush outputs
(* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW, (* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW,
(* mark_debug = "true" *) output logic FlushF, FlushD, FlushE, FlushM, FlushW (* mark_debug = "true" *) output logic FlushD, FlushE, FlushM, FlushW
); );
logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause; logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
@ -89,7 +89,6 @@ module hazard(
assign FirstUnstalledW = ~StallW & StallM; assign FirstUnstalledW = ~StallW & StallM;
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
assign #1 FlushF = BPPredWrongE;
assign #1 FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE; assign #1 FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE;
assign #1 FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor assign #1 FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor
assign #1 FlushM = FirstUnstalledM | TrapM | RetM; assign #1 FlushM = FirstUnstalledM | TrapM | RetM;

4
pipelined/src/ifu/bpred.sv
View File

@ -36,7 +36,7 @@
module bpred module bpred
(input logic clk, reset, (input logic clk, reset,
input logic StallF, StallD, StallE, StallM, input logic StallF, StallD, StallE, StallM,
input logic FlushF, FlushD, FlushE, FlushM, input logic FlushD, FlushE, FlushM,
// Fetch stage // Fetch stage
// the prediction // the prediction
input logic [31:0] InstrD, input logic [31:0] InstrD,
@ -103,7 +103,7 @@ module bpred
else if (`BPTYPE == "BPLOCALPAg") begin:Predictor else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
localHistoryPredictor DirPredictor(.clk, localHistoryPredictor DirPredictor(.clk,
.reset, .StallF, .StallE, .FlushF, .reset, .StallF, .StallE,
.LookUpPC(PCNextF), .LookUpPC(PCNextF),
.Prediction(BPPredF), .Prediction(BPPredF),
// update // update

16
pipelined/src/ifu/ifu.sv
View File

@ -34,7 +34,7 @@
module ifu ( module ifu (
input logic clk, reset, input logic clk, reset,
input logic StallF, StallD, StallE, StallM, input logic StallF, StallD, StallE, StallM,
input logic FlushF, FlushD, FlushE, FlushM, FlushW, input logic FlushD, FlushE, FlushM, FlushW,
// Bus interface // Bus interface
(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR,
@ -113,7 +113,7 @@ module ifu (
logic ICacheFetchLine; logic ICacheFetchLine;
logic BusStall; logic BusStall;
logic ICacheStallF, IFUCacheBusStallF; logic ICacheStallF, IFUCacheBusStallF;
logic CPUBusy; logic GatedStallF;
(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF; (* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF;
// branch predictor signal // branch predictor signal
logic [`XLEN-1:0] PCNext1F, PCNext2F, PCNext0F; logic [`XLEN-1:0] PCNext1F, PCNext2F, PCNext0F;
@ -199,7 +199,7 @@ module ifu (
// The IROM uses untranslated addresses, so it is not compatible with virtual memory. // The IROM uses untranslated addresses, so it is not compatible with virtual memory.
if (`IROM_SUPPORTED) begin : irom if (`IROM_SUPPORTED) begin : irom
assign IFURWF = 2'b10; assign IFURWF = 2'b10;
irom irom(.clk, .reset, .ce(~CPUBusy | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrF)); irom irom(.clk, .reset, .ce(~GatedStallF | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrF));
end else begin end else begin
assign IFURWF = 2'b10; assign IFURWF = 2'b10;
@ -221,7 +221,7 @@ module ifu (
cache #(.LINELEN(`ICACHE_LINELENINBITS), cache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
icache(.clk, .reset, .FlushStage(TrapM), .CPUBusy, icache(.clk, .reset, .FlushStage(TrapM), .Stall(GatedStallF),
.FetchBuffer, .CacheBusAck(ICacheBusAck), .FetchBuffer, .CacheBusAck(ICacheBusAck),
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
.CacheBusRW, .CacheBusRW,
@ -243,7 +243,7 @@ module ifu (
.BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0), .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
.CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0), .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
.FetchBuffer, .PAdr(PCPF), .FetchBuffer, .PAdr(PCPF),
.BusRW, .CPUBusy, .BusRW, .Stall(GatedStallF),
.BusStall, .BusCommitted(BusCommittedF)); .BusStall, .BusCommitted(BusCommittedF));
mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF), mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF),
@ -260,7 +260,7 @@ module ifu (
ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(TrapM), .HRESETn(~reset), .HREADY(IFUHREADY), ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(TrapM), .HRESETn(~reset), .HREADY(IFUHREADY),
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0), .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
.CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); .Stall(GatedStallF), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
assign CacheCommittedF = '0; assign CacheCommittedF = '0;
if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF); if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF);
@ -277,7 +277,7 @@ module ifu (
assign IFUCacheBusStallF = ICacheStallF | BusStall; assign IFUCacheBusStallF = ICacheStallF | BusStall;
assign IFUStallF = IFUCacheBusStallF | SelNextSpillF; assign IFUStallF = IFUCacheBusStallF | SelNextSpillF;
assign CPUBusy = StallF & ~SelNextSpillF; assign GatedStallF = StallF & ~SelNextSpillF;
flopenl #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD); flopenl #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD);
@ -309,7 +309,7 @@ module ifu (
logic [`XLEN-1:0] BPPredPCF; logic [`XLEN-1:0] BPPredPCF;
bpred bpred(.clk, .reset, bpred bpred(.clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallF, .StallD, .StallE, .StallM,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushD, .FlushE, .FlushM,
.InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE, .InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);

4
pipelined/src/ifu/localHistoryPredictor.sv
View File

@ -38,7 +38,7 @@ module localHistoryPredictor
) )
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic StallF, StallE, FlushF, input logic StallF, StallE,
input logic [`XLEN-1:0] LookUpPC, input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] Prediction, output logic [1:0] Prediction,
// update // update
@ -116,7 +116,7 @@ module localHistoryPredictor
flopenrc #(k) LHRFReg(.clk(clk), flopenrc #(k) LHRFReg(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallF), .en(~StallF),
.clear(FlushF), .clear(1'b0),
.d(ForwardLHRNext), .d(ForwardLHRNext),
.q(LHRF)); .q(LHRF));
/* /*

17
pipelined/src/lsu/lsu.sv
View File

@ -103,7 +103,7 @@ module lsu (
logic [6:0] LSUFunct7M; logic [6:0] LSUFunct7M;
logic [1:0] LSUAtomicM; logic [1:0] LSUAtomicM;
(* mark_debug = "true" *) logic [`XLEN+1:0] IHAdrM; (* mark_debug = "true" *) logic [`XLEN+1:0] IHAdrM;
logic CPUBusy; logic GatedStallW;
logic DCacheStallM; logic DCacheStallM;
logic CacheableM; logic CacheableM;
logic BusStall; logic BusStall;
@ -129,18 +129,18 @@ module lsu (
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
hptw hptw(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
.DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
.FlushW, .DCacheStallM, .SATP_REGW, .PCF, .FlushW, .DCacheStallM, .SATP_REGW, .PCF,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
.ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
.IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
.IHAdrM, .CPUBusy, .HPTWStall, .SelHPTW, .IHAdrM, .HPTWStall, .SelHPTW,
.IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, .IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM,
.LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultM); .LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultM);
end else begin end else begin
assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
assign CPUBusy = StallW; assign PreLSURWM = MemRWM; assign PreLSURWM = MemRWM;
assign IHAdrM = IEUAdrExtM; assign IHAdrM = IEUAdrExtM;
assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
assign IHWriteDataM = WriteDataM; assign IHWriteDataM = WriteDataM;
@ -155,6 +155,7 @@ module lsu (
// There is not a clean way to restore back to a partial executed instruction. CommiteedM will // There is not a clean way to restore back to a partial executed instruction. CommiteedM will
// delay the interrupt until the LSU is in a clean state. // delay the interrupt until the LSU is in a clean state.
assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM; assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
assign GatedStallW = StallW & ~SelHPTW;
// MMU and Misalignment fault logic required if privileged unit exists // MMU and Misalignment fault logic required if privileged unit exists
if(`ZICSR_SUPPORTED == 1) begin : dmmu if(`ZICSR_SUPPORTED == 1) begin : dmmu
@ -218,7 +219,7 @@ module lsu (
assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0; assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
// **** fix ReadDataWordM to be LLEN. ByteMask is wrong length. // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
// **** create config to support DTIM with floating point. // **** create config to support DTIM with floating point.
dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM(DTIMMemRWM), dtim dtim(.clk, .reset, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
.Adr(DTIMAdr), .Adr(DTIMAdr),
.FlushW, .WriteDataM(LSUWriteDataM), .FlushW, .WriteDataM(LSUWriteDataM),
.ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0])); .ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
@ -253,7 +254,7 @@ module lsu (
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache( .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache(
.clk, .reset, .CPUBusy, .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
.FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM),
.ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
.CacheWriteData(LSUWriteDataM), .SelHPTW, .CacheWriteData(LSUWriteDataM), .SelHPTW,
@ -269,7 +270,7 @@ module lsu (
.BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM), .WriteDataM(LSUWriteDataM), .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM), .WriteDataM(LSUWriteDataM),
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM, .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM,
.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
.Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy, .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW),
.BusStall, .BusCommitted(BusCommittedM)); .BusStall, .BusCommitted(BusCommittedM));
// FetchBuffer[`AHBW-1:0] needs to be duplicated LLENPOVERAHBW times. // FetchBuffer[`AHBW-1:0] needs to be duplicated LLENPOVERAHBW times.
@ -292,7 +293,7 @@ module lsu (
ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
.HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
.CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM); if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM);
else assign ReadDataWordMuxM = FetchBuffer[`XLEN-1:0]; else assign ReadDataWordMuxM = FetchBuffer[`XLEN-1:0];

4
pipelined/src/mmu/hptw.sv
View File

@ -31,7 +31,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module hptw ( module hptw (
input logic clk, reset, StallW, input logic clk, reset,
input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
input logic [`XLEN-1:0] PCF, // addresses to translate input logic [`XLEN-1:0] PCF, // addresses to translate
input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate
@ -61,7 +61,6 @@ module hptw (
output logic [6:0] LSUFunct7M, output logic [6:0] LSUFunct7M,
output logic IgnoreRequestTLB, output logic IgnoreRequestTLB,
output logic SelHPTW, output logic SelHPTW,
output logic CPUBusy,
output logic HPTWStall, output logic HPTWStall,
input logic LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, input logic LSULoadAccessFaultM, LSUStoreAmoAccessFaultM,
output logic LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultM output logic LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultM
@ -291,7 +290,6 @@ module hptw (
// to the orignal data virtual address. // to the orignal data virtual address.
assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF); assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF);
// always block interrupts when using the hardware page table walker. // always block interrupts when using the hardware page table walker.
assign CPUBusy = StallW & ~SelHPTW;
// multiplex the outputs to LSU // multiplex the outputs to LSU
if(`XLEN == 64) assign HPTWAdrExt = {{(`XLEN+2-`PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits if(`XLEN == 64) assign HPTWAdrExt = {{(`XLEN+2-`PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits

6
pipelined/src/wally/wallypipelinedcore.sv
View File

@ -53,7 +53,7 @@ module wallypipelinedcore (
// logic [1:0] ForwardAE, ForwardBE; // logic [1:0] ForwardAE, ForwardBE;
logic StallF, StallD, StallE, StallM, StallW; logic StallF, StallD, StallE, StallM, StallW;
logic FlushF, FlushD, FlushE, FlushM, FlushW; logic FlushD, FlushE, FlushM, FlushW;
logic RetM; logic RetM;
(* mark_debug = "true" *) logic TrapM; (* mark_debug = "true" *) logic TrapM;
@ -170,7 +170,7 @@ module wallypipelinedcore (
ifu ifu( ifu ifu(
.clk, .reset, .clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallF, .StallD, .StallE, .StallM,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW, .FlushD, .FlushE, .FlushM, .FlushW,
// Fetch // Fetch
.HRDATA, .PCF, .IFUHADDR, .HRDATA, .PCF, .IFUHADDR,
.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE,
@ -325,7 +325,7 @@ module wallypipelinedcore (
.wfiM, .IntPendingM, .wfiM, .IntPendingM,
// Stall & flush outputs // Stall & flush outputs
.StallF, .StallD, .StallE, .StallM, .StallW, .StallF, .StallD, .StallE, .StallM, .StallW,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW .FlushD, .FlushE, .FlushM, .FlushW
); // global stall and flush control ); // global stall and flush control
if (`ZICSR_SUPPORTED) begin:priv if (`ZICSR_SUPPORTED) begin:priv