mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
fixed subtle typo in icache fsm. Was messing up hit spill hit.
I believe the mibench qsort benchmark runs after this icache fix.
This commit is contained in:
Ross Thompson
parent
0a44d4dd4e
commit
ed4f2ecb24
@ -24,11 +24,15 @@
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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///////////////////////////////////////////
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// RV32 or RV64: XLEN = 32 or 64
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`define BUILDROOT 0
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`define BUSYBEAR 0
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// RV32 or RV64: XLEN = 32 or 64
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 64
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`define XLEN 64
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//`define MISA (32'h00000104)
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//`define MISA (32'h00000105)
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`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20)
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`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0)
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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@ -54,7 +58,8 @@
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`define MEM_DCACHE 0
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`define MEM_DCACHE 0
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`define MEM_DTIM 1
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`define MEM_DTIM 1
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`define MEM_ICACHE 0
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`define MEM_ICACHE 0
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`define MEM_VIRTMEM 0
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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// Address space
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// Address space
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`define RESET_VECTOR 64'h0000000000000000
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`define RESET_VECTOR 64'h0000000000000000
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@ -69,20 +74,20 @@
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`define BOOTTIMBASE 32'h00800000
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`define BOOTTIMBASE 32'h00800000
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`define BOOTTIMRANGE 32'h00003FFF
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`define BOOTTIMRANGE 32'h00003FFF
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`define TIMBASE 32'h00000000
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`define TIMBASE 32'h00000000
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`define TIMRANGE 32'h007FFFFF
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`define TIMRANGE 32'h07FFFFFF
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`define CLINTBASE 32'h02000000
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`define CLINTBASE 32'h02000000
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`define CLINTRANGE 32'h0000FFFF
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`define CLINTRANGE 32'h0000FFFF
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`define GPIOBASE 32'h10012000
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`define GPIOBASE 32'h10012000
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`define GPIORANGE 32'h000000FF
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`define GPIORANGE 32'h000000FF
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`define UARTBASE 32'h10000000
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`define UARTBASE 32'h10000000
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`define UARTRANGE 32'h00000007
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`define UARTRANGE 32'h00000007
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`define PLICBASE 32'h0C000000
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`define PLICBASE 32'h0C000000
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`define PLICRANGE 32'h03FFFFFF
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`define PLICRANGE 32'h03FFFFFF
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// Test modes
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// Test modes
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// Tie GPIO outputs back to inputs
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 0
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`define GPIO_LOOPBACK_TEST 1
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// Busybear special CSR config to match OVPSim
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// Busybear special CSR config to match OVPSim
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`define OVPSIM_CSR_CONFIG 0
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`define OVPSIM_CSR_CONFIG 0
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@ -90,6 +95,13 @@
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// Hardware configuration
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// Hardware configuration
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`define UART_PRESCALE 1
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`define UART_PRESCALE 1
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// Interrupt configuration
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`define PLIC_NUM_SRC 4
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// comment out the following if >=32 sources
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`define PLIC_NUM_SRC_LT_32
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`define PLIC_GPIO_ID 3
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`define PLIC_UART_ID 4
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/* verilator lint_off STMTDLY */
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/* verilator lint_off STMTDLY */
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off ASSIGNDLY */
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@ -26,6 +26,8 @@
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///////////////////////////////////////////
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///////////////////////////////////////////
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// Virtual Memory Constants (sv39)
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// Virtual Memory Constants (sv39)
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`define VPN_SEGMENT_BITS 9
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`define VPN_BITS 27
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`define VPN_BITS 27
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`define PPN_BITS 44
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`define PPN_BITS 44
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`define PPN_HIGH_SEGMENT_BITS 26
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`define PA_BITS 56
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`define PA_BITS 56
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@ -1,5 +1,4 @@
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onerror {resume}
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onerror {resume}
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quietly virtual function -install /testbench/dut/hart/ifu/icache/cachemem -env /testbench/dut/hart/ifu/icache/cachemem { &{/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[4], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[3], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[2], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[1], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[0] }} offset
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quietly WaveActivateNextPane {} 0
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset
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@ -8,68 +7,68 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DataStall
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/DataStall
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPPredF
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add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPPredF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF
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add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF
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add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF
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add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF
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add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF
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add wave -noupdate -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePC
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add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePC
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add wave -noupdate -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdateEN
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add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdateEN
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add wave -noupdate -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePrediction
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add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePrediction
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC
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add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -expand -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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@ -89,18 +88,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
|
|||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
|
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
|
||||||
add wave -noupdate -group alu -divider internals
|
add wave -noupdate -expand -group alu -divider internals
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
|
||||||
add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemReadM
|
add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemReadM
|
||||||
add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemWriteM
|
add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemWriteM
|
||||||
add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemAckW
|
add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemAckW
|
||||||
@ -158,9 +157,9 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
|
|||||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
|
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
|
||||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
|
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
|
||||||
add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
|
add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||||
|
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
|
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
|
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||||
@ -177,28 +176,21 @@ add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/i
|
|||||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/WORDSPERLINE
|
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/WORDSPERLINE
|
||||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LOGWPL
|
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LOGWPL
|
||||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LINESIZE
|
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LINESIZE
|
||||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
|
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
|
||||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
|
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
|
||||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
||||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
||||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
|
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
|
||||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
|
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
|
||||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWritePAdr
|
add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
|
add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid
|
add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadTag
|
add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag
|
add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadAddr
|
add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
|
add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadPAdr
|
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
|
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
|
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WritePAdr
|
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteSet
|
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteTag
|
|
||||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
|
|
||||||
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
|
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
|
||||||
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD
|
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD
|
||||||
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FlushDLastCyclen
|
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FlushDLastCyclen
|
||||||
@ -223,12 +215,11 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
|
|||||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
||||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF
|
add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
|
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 2} {9951515 ns} 0} {{Cursor 4} {1318991 ns} 0}
|
WaveRestoreCursors {{Cursor 2} {252630976 ns} 1} {{Cursor 4} {72696935 ns} 0} {{Cursor 3} {252631405 ns} 0}
|
||||||
quietly wave cursor active 1
|
quietly wave cursor active 1
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 513
|
configure wave -valuecolwidth 189
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
configure wave -signalnamewidth 1
|
configure wave -signalnamewidth 1
|
||||||
configure wave -snapdistance 10
|
configure wave -snapdistance 10
|
||||||
@ -241,4 +232,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {9951431 ns} {9951599 ns}
|
WaveRestoreZoom {252630882 ns} {252631198 ns}
|
||||||
|
|||||||
@ -216,14 +216,13 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
|||||||
// Cache fault signals
|
// Cache fault signals
|
||||||
//logic FaultStall;
|
//logic FaultStall;
|
||||||
|
|
||||||
//flopenl #(`XLEN) PCPFFlop(clk, reset, SavePC & ~StallF, PCPFinalF, `RESET_VECTOR, PCPF);
|
|
||||||
// on spill we want to get the first 2 bytes of the next cache block.
|
// on spill we want to get the first 2 bytes of the next cache block.
|
||||||
// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
|
// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
|
||||||
// simply add 2 to land on the next cache block.
|
// simply add 2 to land on the next cache block.
|
||||||
assign PCSpillF = PCPF + 2'b10;
|
assign PCSpillF = PCPF + 2'b10;
|
||||||
|
|
||||||
// now we have to select between these three PCs
|
// now we have to select between these three PCs
|
||||||
assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf
|
assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary
|
||||||
assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF;
|
assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF;
|
||||||
|
|
||||||
// this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later.
|
// this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later.
|
||||||
@ -283,7 +282,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
|||||||
end else if (~hit & ~spill) begin
|
end else if (~hit & ~spill) begin
|
||||||
CntReset = 1'b1;
|
CntReset = 1'b1;
|
||||||
NextState = STATE_MISS_FETCH_WDV;
|
NextState = STATE_MISS_FETCH_WDV;
|
||||||
end else if (~hit & spill) begin
|
end else if (~hit & spill) begin
|
||||||
CntReset = 1'b1;
|
CntReset = 1'b1;
|
||||||
PCMux = 2'b10;
|
PCMux = 2'b10;
|
||||||
NextState = STATE_MISS_SPILL_FETCH_WDV;
|
NextState = STATE_MISS_SPILL_FETCH_WDV;
|
||||||
@ -299,9 +298,10 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
|||||||
ICacheReadEn = 1'b1;
|
ICacheReadEn = 1'b1;
|
||||||
if (hit) begin
|
if (hit) begin
|
||||||
NextState = STATE_HIT_SPILL_FINAL;
|
NextState = STATE_HIT_SPILL_FINAL;
|
||||||
end else
|
end else begin
|
||||||
CntReset = 1'b1;
|
CntReset = 1'b1;
|
||||||
NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
|
NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
STATE_HIT_SPILL_MISS_FETCH_WDV: begin
|
STATE_HIT_SPILL_MISS_FETCH_WDV: begin
|
||||||
PCMux = 2'b10;
|
PCMux = 2'b10;
|
||||||
@ -424,16 +424,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
|||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
// fsm outputs
|
|
||||||
// stall CPU any time we are not in the ready state. any other state means the
|
|
||||||
// cache is either requesting data from the memory interface or handling a
|
|
||||||
// spill over two cycles.
|
|
||||||
// *** BUG this logic will need to change
|
|
||||||
//assign ICacheStallF = ((CurrState != STATE_READY) | ~hit | spill) | reset_q ? 1'b1 : 1'b0;
|
|
||||||
// save the PC anytime we are in the ready state. The saved value will be used as the PC may not be stable.
|
|
||||||
//assign SavePC = ((CurrState == STATE_READY) & hit) & ~spill ? 1'b1 : 1'b0;
|
|
||||||
assign CntEn = PreCntEn & InstrAckF;
|
assign CntEn = PreCntEn & InstrAckF;
|
||||||
|
|
||||||
assign InstrReadF = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
|
assign InstrReadF = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
|
||||||
(CurrState == STATE_MISS_FETCH_WDV) ||
|
(CurrState == STATE_MISS_FETCH_WDV) ||
|
||||||
(CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
|
(CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
|
||||||
@ -456,7 +447,6 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
|||||||
// we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros.
|
// we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros.
|
||||||
// fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with
|
// fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with
|
||||||
// more zeros after the addition. This will be the number of offset bits less the AHBByteLength.
|
// more zeros after the addition. This will be the number of offset bits less the AHBByteLength.
|
||||||
// *** now a bug need to mux between PCPF and PCPF+2
|
|
||||||
assign InstrPAdrF = {{PCPTrunkF, {{LOGWPL}{1'b0}}} + FetchCount, {{OFFSETWIDTH-LOGWPL}{1'b0}}};
|
assign InstrPAdrF = {{PCPTrunkF, {{LOGWPL}{1'b0}}} + FetchCount, {{OFFSETWIDTH-LOGWPL}{1'b0}}};
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user