diff --git a/src/fpu/packoutput.sv b/src/fpu/packoutput.sv
index a81527e01..e83f403c5 100644
--- a/src/fpu/packoutput.sv
+++ b/src/fpu/packoutput.sv
@@ -100,4 +100,4 @@ module packoutput import cvw::*;  #(parameter cvw_t P) (
       endcase
     end
   end
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/kmu/zbkb.sv b/src/ieu/kmu/zbkb.sv
index 61173e982..bd0048526 100644
--- a/src/ieu/kmu/zbkb.sv
+++ b/src/ieu/kmu/zbkb.sv
@@ -43,7 +43,7 @@ module zbkb #(parameter WIDTH=32) (
          assign Brev8Result[i*8+j] = A[i*8+7-j];
    
    packer #(WIDTH) pack(.A, .B, .PackSelect({ZBKBSelect[2], Funct3[1:0]}), .PackResult);
-   zipper #(WIDTH) zip(.A, .ZipSelect(Funct3[2]), .ZipResult);
+   zipper #(WIDTH) zipper(.A, .ZipSelect(Funct3[2]), .ZipResult);
    
    // ZBKB Result Select Mux
    mux3 #(WIDTH) zbkbresultmux(Brev8Result, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult);   
diff --git a/testbench/wallywrapper.sv b/testbench/wallywrapper.sv
index 990ebfe74..2794240be 100644
--- a/testbench/wallywrapper.sv
+++ b/testbench/wallywrapper.sv
@@ -26,14 +26,18 @@
 
 `include "config.vh"
 
-import cvw::*;
 
-module wallywrapper;
+
+module wallywrapper import cvw::*;(
+  input logic clk,
+  input logic reset_ext,
+  input logic SPIIn,
+  input logic SDCIntr
+);
  
 `include "parameter-defs.vh"
 
-  logic        clk;
-  logic        reset_ext, reset;
+  logic        reset;
 
   logic [P.AHBW-1:0]    HRDATAEXT;
   logic                HREADYEXT, HRESPEXT;
@@ -50,9 +54,8 @@ module wallywrapper;
 
   logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
   logic        UARTSin, UARTSout;
-  logic        SPIIn, SPIOut;
+  logic        SPIOut;
   logic [3:0]  SPICS;
-  logic        SDCIntr;
 
   logic        HREADY;
   logic        HSELEXT;