mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Moved the simple branch predictor custom test into the gshare.S
coverage test.
This commit is contained in:
Rose Thompson
parent
a56ef9e267
commit
ebdef07301
@ -1,3 +1,54 @@
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///////////////////////////////////////////
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// gshare.S
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//
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// Written: Rose Thompson rose@rosethompson.net
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//
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// Purpose: basic check that global history and gshare branch npredictors are working as expected. Requires manual inspection.
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// TODO: *** Automate checking prediction accuracy.
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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# run-elf.bash find this in project description
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main:
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addi sp, sp, 8
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sd ra, 0(sp)
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jal ra, oneLoopTest
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jal ra, global_hist_6_space_test
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jal ra, global_hist_4_space_test
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jal ra, global_hist_3_space_test
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jal ra, global_hist_2_space_test
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jal ra, global_hist_1_space_test
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jal ra, global_hist_0_space_test
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fence.I
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finished:
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j done
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.data
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.section .text
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.globl oneLoopTest
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.type oneLoopTest, @function
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@ -1,19 +0,0 @@
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TARGETDIR := simple
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TARGET := $(TARGETDIR)/$(TARGETDIR).elf
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ROOT := ..
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LIBRARY_DIRS := ${ROOT}/crt0
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LIBRARY_FILES := crt0
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MARCH :=-march=rv64imfdczicbom
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MABI :=-mabi=lp64d
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LINKER := ${ROOT}/linker8000-0000.x
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LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib
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CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2
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CC=riscv64-unknown-elf-gcc
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DA=riscv64-unknown-elf-objdump -d
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include $(ROOT)/makefile.inc
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@ -1,449 +0,0 @@
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# Written: ross1728@gmail.com Rose Thompson 17 August 2023
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# Modified:
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# Purpose: Tests the 3 Zicbom cache instructions which all operate on cacheline
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# granularity blocks of memory. Invalidate: Clears valid and dirty bits
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# and does not write back. Clean: Writes back dirty cacheline if needed
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# and clears dirty bit. Does NOT clear valid bit. Flush: Cleans and then
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# Invalidates. These operations apply to all caches in the memory system.
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# The tests are divided into three parts one for the data cache, instruction cache
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# and checks to verify the uncached regions of memory cause exceptions.
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# -----------
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# Copyright (c) 2020. RISC-V International. All rights reserved.
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# SPDX-License-Identifier: BSD-3-Clause
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# -----------
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#
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# This assembly file tests the fence.i instruction of the RISC-V Zifencei extension.
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#
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.section .text
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.globl CBOMTest
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.type CBOMTest, @function
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CBOMTest:
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# *** TODO
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# first need to discover the length of the cacheline.
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# for now assume it is 64 bytes
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addi sp, sp, -16
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sd s0, 0(sp)
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sd ra, 8(sp)
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la s0, signature
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################################################################################
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# INVALIDATE D$
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################################################################################
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# theory of operation
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# 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
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# 2. Then verify the second region has the same data
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# 3. Invalidate the second region
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# 4. Verify the second region has the original invalid data
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# DON'T batch each step. We want to see the transition between cachelines. The current should be invalidated
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# but the next should have the copied data.
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# step 1
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CBOMTest_inval_step1:
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la a0, SourceData
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la a1, Destination1
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li a2, 64
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jal ra, memcpy8
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# step 2
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CBOMTest_inval_step2:
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la a0, SourceData
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la a1, Destination1
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 3
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CBOMTest_inval_step3:
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la a1, Destination1
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cbo.inval (a1)
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# step 4 (should be Invalid)
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la a0, DeadBeafData1
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la a1, Destination1
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li a2, 8
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 4 next line (should still be valid)
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CBOMTest_inval_step4:
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la a0, SourceData+64
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la a1, Destination1+64
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li a2, 8
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 3 (Invalidate all remaining lines)
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CBOMTest_inval_step3_all:
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la a1, Destination1+64
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cbo.inval (a1)
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cbo.inval (a1) # verify invalidating an already non present line does not cause an issue.
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la a1, Destination1+128
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cbo.inval (a1)
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la a1, Destination1+192
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cbo.inval (a1)
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la a1, Destination1+256
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cbo.inval (a1)
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la a1, Destination1+320
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cbo.inval (a1)
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la a1, Destination1+384
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cbo.inval (a1)
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la a1, Destination1+448
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cbo.inval (a1)
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# step 4 All should be invalid
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CBOMTest_inval_step4_all:
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la a0, DeadBeafData1
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la a1, Destination1
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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################################################################################
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# Clean D$
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################################################################################
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# theory of operation
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# 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
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# 2. Then verify the second region has the same data
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# 3. Invalidate the second region
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# 4. Verify the second region has the original invalid data
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# 5. Repeat step 1
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# 6. Clean cachelines
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# 7. Verify the second region has the same data
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# 8. Invalidate the second region
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# 9. Verify again but this time it should contain the same data
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# DON'T batch each step. We want to see the transition between cachelines. The current should be invalidated
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# but the next should have the copied data.
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# step 1
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CBOMTest_clean_step1:
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la a0, SourceData
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la a1, Destination2
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li a2, 64
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jal ra, memcpy8
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# step 2
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CBOMTest_clean_step2:
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la a0, SourceData
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la a1, Destination2
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 3
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CBOMTest_clean_step3:
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la a1, Destination2
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cbo.inval (a1)
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la a1, Destination2+64
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cbo.inval (a1)
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la a1, Destination2+128
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cbo.inval (a1)
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la a1, Destination2+192
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cbo.inval (a1)
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la a1, Destination2+256
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cbo.inval (a1)
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la a1, Destination2+320
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cbo.inval (a1)
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la a1, Destination2+384
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cbo.inval (a1)
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la a1, Destination2+448
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cbo.inval (a1)
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cbo.inval (a1)
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cbo.inval (a1)
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cbo.inval (a1)
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cbo.inval (a1)
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cbo.inval (a1)
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cbo.inval (a1)
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cbo.inval (a1)
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cbo.inval (a1)
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cbo.inval (a1)
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# step 4 All should be invalid
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CBOMTest_clean_step4:
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la a0, DeadBeafData1
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la a1, Destination2
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 5
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CBOMTest_clean_step5:
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la a0, SourceData
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la a1, Destination2
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li a2, 64
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jal ra, memcpy8
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# step 6 only clean 1 line
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CBOMTest_clean_step6:
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la a1, Destination2
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cbo.clean (a1)
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# step 7 only check that 1 line
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CBOMTest_clean_step7:
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la a0, SourceData
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la a1, Destination2
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li a2, 8
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 8 invalidate that 1 line and the next
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CBOMTest_clean_step8:
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la a1, Destination2
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cbo.inval (a1)
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la a1, Destination2+64
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cbo.inval (a1)
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# step 9 that 1 line should contain the valid data
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CBOMTest_clean_step9_line1:
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la a0, SourceData
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la a1, Destination2
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li a2, 8
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 9 the next should contain the invalid data
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CBOMTest_clean_step9_line2:
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la a0, DeadBeafData1
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la a1, Destination2+64
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li a2, 8
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 5 # now recopy the one we just corrupted
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CBOMTest_clean_step5_recopy_line2:
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la a0, SourceData+64
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la a1, Destination2+64
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li a2, 8
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jal ra, memcpy8
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# step 6 # clean the remaining
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CBOMTest_clean_step6_clean_all:
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la a1, Destination2+64
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cbo.clean (a1)
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la a1, Destination2+128
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cbo.clean (a1)
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la a1, Destination2+192
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cbo.clean (a1)
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la a1, Destination2+256
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cbo.clean (a1)
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la a1, Destination2+320
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cbo.clean (a1)
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la a1, Destination2+384
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cbo.clean (a1)
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la a1, Destination2+448
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cbo.clean (a1)
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cbo.clean (a1)
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cbo.clean (a1)
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cbo.clean (a1)
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cbo.clean (a1)
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cbo.clean (a1)
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cbo.clean (a1)
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cbo.clean (a1)
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cbo.clean (a1)
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# step 8 # invalidate all remaining
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CBOMTest_clean_step7_invalidate_all:
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la a1, Destination2
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cbo.inval (a1)
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la a1, Destination2+64
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cbo.inval (a1)
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la a1, Destination2+128
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cbo.inval (a1)
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la a1, Destination2+192
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cbo.inval (a1)
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la a1, Destination2+256
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cbo.inval (a1)
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la a1, Destination2+320
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cbo.inval (a1)
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la a1, Destination2+384
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cbo.inval (a1)
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la a1, Destination2+448
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cbo.inval (a1)
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# step 9 # check all
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CBOMTest_clean_step9_check_all:
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la a0, SourceData
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la a1, Destination2
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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################################################################################
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# Flush D$ line
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################################################################################
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# theory of operation
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# 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
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# 2. Then verify the second region has the same data
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# 3. For flush there is no way to create a negative control. We will flush 1 cache line
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# 4. Verify whole region
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# 5. Flush the remaining lines
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# 6. Verify whole region
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# step 1
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CBOMTest_flush_step1:
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la a0, SourceData
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la a1, Destination3
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li a2, 64
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jal ra, memcpy8
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# step 2 All should be valid
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CBOMTest_flush_step2_verify:
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la a0, SourceData
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la a1, Destination3
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 3 # flush 1 line
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CBOMTest_flush_step3:
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la a1, Destination3
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cbo.flush (a1)
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# step 4
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CBOMTest_flush_step4_verify:
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la a0, SourceData
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la a1, Destination3
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 5
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CBOMTest_flush_step5_flush_all:
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la a1, Destination3
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cbo.flush (a1)
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la a1, Destination3+64
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cbo.flush (a1)
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la a1, Destination3+128
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cbo.flush (a1)
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la a1, Destination3+192
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cbo.flush (a1)
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la a1, Destination3+256
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cbo.flush (a1)
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la a1, Destination3+320
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cbo.flush (a1)
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la a1, Destination3+384
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cbo.flush (a1)
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la a1, Destination3+448
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cbo.flush (a1)
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cbo.flush (a1)
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cbo.flush (a1)
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cbo.flush (a1)
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cbo.flush (a1)
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cbo.flush (a1)
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# step 6
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CBOMTest_flush_step6_verify:
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la a0, SourceData
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la a1, Destination3
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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ld s0, 0(sp)
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ld ra, 8(sp)
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addi sp, sp, 16
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ret
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.section .text
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.type memcpy8, @function
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memcpy8:
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# a0 is the source
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# a1 is the dst
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# a2 is the number of 8 byte words
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mv t0, a0
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mv t1, a1
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li t2, 0
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memcpy8_loop:
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ld t3, 0(t0)
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sd t3, 0(t1)
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addi t0, t0, 8
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addi t1, t1, 8
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addi t2, t2, 1
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blt t2, a2, memcpy8_loop
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ret
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.section .text
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.type memcmp8, @function
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# returns which index mismatch, -1 if none
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memcmp8:
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# a0 is the source1
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# a1 is the source2
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# a2 is the number of 8 byte words
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mv t0, a0
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mv t1, a1
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li t2, 0
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memcmp8_loop:
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ld t3, 0(t0)
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ld t4, 0(t1)
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bne t3, t4, memcmp8_ne
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addi t0, t0, 8
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addi t1, t1, 8
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addi t2, t2, 1
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blt t2, a2, memcmp8_loop
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li a0, -1
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ret
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memcmp8_ne:
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mv a0, t2
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ret
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.data
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.align 7
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DeadBeafData1:
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.fill 64, 8, 0xdeadbeefdeadbeef
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SourceData:
|
||||
.int 0, 1, 2, 3, 4, 5, 6, 7
|
||||
.int 8, 9, 10, 11, 12, 13, 14, 15
|
||||
.int 16, 17, 18, 19, 20, 21, 22, 23
|
||||
.int 24, 25, 26, 27, 28, 29, 30, 31
|
||||
.int 32, 33, 34, 35, 36, 37, 38, 39
|
||||
.int 40, 41, 42, 43, 44, 45, 46, 47
|
||||
.int 48, 49, 50, 51, 52, 53, 54, 55
|
||||
.int 56, 57, 58, 59, 60, 61, 62, 63
|
||||
.int 64, 65, 66, 67, 68, 69, 70, 71
|
||||
.int 72, 73, 74, 75, 76, 77, 79, 79
|
||||
.int 80, 81, 82, 83, 84, 85, 86, 87
|
||||
.int 88, 89, 90, 91, 92, 93, 94, 95
|
||||
.int 96, 97, 98, 99, 100, 101, 102, 103
|
||||
.int 104, 105, 106, 107, 108, 109, 110, 111
|
||||
.int 112, 113, 114, 115, 116, 117, 118, 119
|
||||
.int 120, 121, 122, 123, 124, 125, 126, 127
|
||||
|
||||
Destination1:
|
||||
.fill 64, 8, 0xdeadbeefdeadbeef
|
||||
Destination2:
|
||||
.fill 64, 8, 0xdeadbeefdeadbeef
|
||||
Destination3:
|
||||
.fill 64, 8, 0xdeadbeefdeadbeef
|
||||
Destination4:
|
||||
.fill 64, 8, 0xdeadbeefdeadbeef
|
||||
|
||||
signature:
|
||||
.fill 16, 8, 0x0bad0bad0bad0bad
|
||||
|
||||
|
||||
ExceptedSignature:
|
||||
.fill 13, 8, 0xFFFFFFFFFFFFFFFF
|
||||
.fill 3, 8, 0x0bad0bad0bad0bad
|
||||
|
||||
@ -1,11 +0,0 @@
|
||||
# Rose Thompson
|
||||
# March 17, 2021
|
||||
# Oklahoma State University
|
||||
|
||||
.section .text
|
||||
.global fail
|
||||
.type fail, @function
|
||||
fail:
|
||||
li gp, 1
|
||||
li a0, -1
|
||||
ecall
|
||||
@ -1,16 +0,0 @@
|
||||
#ifndef __header
|
||||
#define __header
|
||||
|
||||
int fail();
|
||||
int simple_csrbr_test();
|
||||
int lbu_test();
|
||||
int icache_spill_test();
|
||||
void global_hist_0_space_test();
|
||||
void global_hist_1_space_test();
|
||||
void global_hist_2_space_test();
|
||||
void global_hist_3_space_test();
|
||||
void global_hist_4_space_test();
|
||||
void global_hist_6_space_test();
|
||||
void oneLoopTest();
|
||||
void CBOMTest();
|
||||
#endif
|
||||
@ -1,19 +0,0 @@
|
||||
.section .text
|
||||
.global lbu_test
|
||||
.type lbu_test, @function
|
||||
|
||||
lbu_test:
|
||||
|
||||
li t0, 0x80000
|
||||
lbu t1, 0(t0)
|
||||
|
||||
|
||||
pass:
|
||||
li a0, 0
|
||||
done:
|
||||
ret
|
||||
|
||||
fail:
|
||||
li a0, -1
|
||||
j done
|
||||
|
||||
@ -1,25 +0,0 @@
|
||||
#include "header.h"
|
||||
|
||||
int main(){
|
||||
//int res = icache_spill_test();
|
||||
oneLoopTest();
|
||||
global_hist_6_space_test();
|
||||
global_hist_4_space_test();
|
||||
global_hist_3_space_test();
|
||||
global_hist_2_space_test();
|
||||
global_hist_1_space_test();
|
||||
global_hist_0_space_test();
|
||||
CBOMTest();
|
||||
int res = 1;
|
||||
if (res < 0) {
|
||||
fail();
|
||||
return 0;
|
||||
}else {
|
||||
if((res = lbu_test()) < 0) {
|
||||
fail();
|
||||
return 0;
|
||||
}
|
||||
res = simple_csrbr_test();
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
@ -1,62 +0,0 @@
|
||||
.section .text
|
||||
.global simple_csrbr_test
|
||||
.type simple_csrbr_test, @function
|
||||
|
||||
simple_csrbr_test:
|
||||
|
||||
# step 1 enable the performance counters
|
||||
# by default the hardware enables all performance counters
|
||||
# however we will eventually want to manually enable incase
|
||||
# some other code disables them
|
||||
|
||||
# br count is counter 5
|
||||
# br mp count is counter 4
|
||||
li t0, 0x30
|
||||
|
||||
csrrc x0, 0x320, t0 # clear bits 4 and 5 of inhibit register.
|
||||
|
||||
# step 2 read performance counters into general purpose registers
|
||||
|
||||
csrrw t2, 0xB05, x0 # t2 = BR COUNT (perf count 5)
|
||||
csrrw t3, 0xB04, x0 # t3 = BRMP COUNT (perf count 4)
|
||||
|
||||
# step 3 simple loop to show the counters are updated.
|
||||
li t0, 0 # this is the loop counter
|
||||
li t1, 100 # this is the loop end condition
|
||||
|
||||
# for(t1 = 0; t1 < t0; t1++);
|
||||
|
||||
loop:
|
||||
addi t0, t0, 1
|
||||
blt t0, t1, loop
|
||||
|
||||
loop_done:
|
||||
|
||||
# step 2 read performance counters into general purpose registers
|
||||
|
||||
csrrw t4, 0xB05, x0 # t4 = BR COUNT (perf count 5)
|
||||
csrrw t5, 0xB04, x0 # t5 = BRMP COUNT (perf count 4)
|
||||
|
||||
sub t2, t4, t2 # this is the number of branch instructions committed.
|
||||
sub t3, t5, t3 # this is the number of branch mispredictions committed.
|
||||
|
||||
# now check if the branch count equals 100 and if the branch
|
||||
bne t4, t2, fail
|
||||
li t5, 3
|
||||
bne t3, t5, fail
|
||||
|
||||
pass:
|
||||
li a0, 0
|
||||
done:
|
||||
li t0, 0x30
|
||||
csrrs x0, 0x320, t0 # set bits 4 and 5
|
||||
ecall
|
||||
ret
|
||||
|
||||
fail:
|
||||
li a0, -1
|
||||
j done
|
||||
|
||||
.data
|
||||
sample_data:
|
||||
.int 0
|
||||
Loading…
Reference in New Issue
Block a user