From ebcffcdebd027b072af29cd910c7b9b37d99711b Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 18 Dec 2021 09:27:25 -0800
Subject: [PATCH] Moved W64 truncation after result mux

---
 wally-pipelined/src/ieu/alu.sv      | 34 +++++++++++++----------------
 wally-pipelined/src/ieu/datapath.sv |  6 ++---
 2 files changed, 17 insertions(+), 23 deletions(-)

diff --git a/wally-pipelined/src/ieu/alu.sv b/wally-pipelined/src/ieu/alu.sv
index e2dd7eef6..1d49bb401 100644
--- a/wally-pipelined/src/ieu/alu.sv
+++ b/wally-pipelined/src/ieu/alu.sv
@@ -32,7 +32,7 @@ module alu #(parameter WIDTH=32) (
   output logic [WIDTH-1:0] Result,
   output logic [WIDTH-1:0] Sum);
 
-  logic [WIDTH-1:0] CondInvB, SumTrunc, Shift, SLT, SLTU, bor;
+  logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
   logic        Right;
   logic        Carry, Neg;
   logic        LT, LTU;
@@ -50,17 +50,7 @@ module alu #(parameter WIDTH=32) (
   assign CondInvB = SubArith ? ~B : B;
   assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
   
-  // support W-type RV64I ADDW/SUBW/ADDIW that sign-extend 32-bit result to 64 bits
-  generate
-    if (WIDTH==64)
-      assign SumTrunc = W64 ? {{32{Sum[31]}}, Sum[31:0]} : Sum;
-    else
-      assign SumTrunc = Sum;
-  endgenerate
-  
   // Shifts
-  // assign arith = alucontrol[3]; // sra
-  // assign w64 = alucontrol[4];
   assign Right = (Funct3[2:0] == 3'b101); // sra or srl
   shifter sh(A, B[5:0], Right, SubArith, W64, Shift);
   
@@ -80,14 +70,20 @@ module alu #(parameter WIDTH=32) (
   assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
   always_comb
     case (ALUFunct)
-      3'b000: Result = SumTrunc;  // add or sub
-      3'b001: Result = Shift;     // sll
-      3'b010: Result = SLT;       // slt
-      3'b011: Result = SLTU;      // sltu
-      3'b100: Result = A ^ B;     // xor
-      3'b101: Result = Shift;     // sra or srl
-      3'b110: Result = A | B;     // or 
-      3'b111: Result = A & B;     // and
+      3'b000: FullResult = Sum;       // add or sub
+      3'b001: FullResult = Shift;     // sll
+      3'b010: FullResult = SLT;       // slt
+      3'b011: FullResult = SLTU;      // sltu
+      3'b100: FullResult = A ^ B;     // xor
+      3'b101: FullResult = Shift;     // sra or srl
+      3'b110: FullResult = A | B;     // or 
+      3'b111: FullResult = A & B;     // and
     endcase
+
+  // support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits
+  generate
+    if (WIDTH==64)  assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
+    else            assign Result = FullResult;
+  endgenerate
 endmodule
 
diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index 9ad32acbb..c36077d21 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -136,9 +136,7 @@ module datapath (
 
   // handle Store Conditional result if atomic extension supported
   generate
-    if (`A_SUPPORTED)
-      assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW};
-    else 
-      assign SCResultW = 0;
+    if (`A_SUPPORTED) assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW};
+    else              assign SCResultW = 0;
   endgenerate
 endmodule