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manually resolved git merge conflicts in testbench linux after checkpointing
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.gitignore.gitmodulesREADME.md
tests/riscv-coremark
.gitignore.gitmodulesLICENSEREADME.mdbuild-coremark.sh
coremark
LICENSE.mdMakefileREADME.md
barebones
core_list_join.ccore_main.ccore_matrix.ccore_state.ccore_util.ccoremark.hcoremark.md5cygwin
docs
READM.mdbalance_O0_joined.pngindex.html
html
files
PIC32
core_list_join-c.htmlcore_main-c.htmlcore_matrix-c.htmlcore_state-c.htmlcore_util-c.htmlcoremark-h.htmldocs
linux
readme-txt.htmlrelease_notes-txt.htmlindex
BuildTargets.htmlConfiguration.htmlConfigurations.htmlFiles.htmlFunctions.htmlGeneral.htmlGeneral2.htmlTypes.htmlVariables.html
javascript
search
BuildTargetsP.htmlConfigurationC.htmlConfigurationH.htmlConfigurationM.htmlConfigurationS.htmlConfigurationT.htmlConfigurationU.htmlConfigurationsH.htmlConfigurationsM.htmlConfigurationsS.htmlConfigurationsT.htmlFilesC.htmlFilesR.htmlFunctionsC.htmlFunctionsG.htmlFunctionsI.htmlFunctionsM.htmlFunctionsP.htmlFunctionsS.htmlFunctionsT.htmlGeneralB.htmlGeneralC.htmlGeneralD.htmlGeneralF.htmlGeneralG.htmlGeneralH.htmlGeneralI.htmlGeneralL.htmlGeneralM.htmlGeneralO.htmlGeneralP.htmlGeneralR.htmlGeneralS.htmlGeneralT.htmlGeneralU.htmlGeneralV.htmlGeneralW.htmlNoResults.htmlTypesS.htmlVariablesC.htmlVariablesD.htmlVariablesL.htmlVariablesO.htmlVariablesP.htmlVariablesR.htmlVariablesS.html
styles
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.gitignore
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4
.gitignore
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@ -6,6 +6,9 @@
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__pycache__/
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__pycache__/
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.vscode/
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.vscode/
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#External repos
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addins
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#vsim work files to ignore
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#vsim work files to ignore
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transcript
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transcript
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vsim.wlf
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vsim.wlf
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@ -38,4 +41,5 @@ wally-pipelined/linux-testgen/buildroot-config-src/main.config.old
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wally-pipelined/linux-testgen/buildroot-config-src/linux.config.old
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wally-pipelined/linux-testgen/buildroot-config-src/linux.config.old
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wally-pipelined/linux-testgen/buildroot-config-src/busybox.config.old
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wally-pipelined/linux-testgen/buildroot-config-src/busybox.config.old
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wally-pipelined/regression/slack-notifier/slack-webhook-url.txt
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wally-pipelined/regression/slack-notifier/slack-webhook-url.txt
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wally-pipelined/regression/logs
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3
.gitmodules
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3
.gitmodules
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[submodule "sky130/sky130_osu_sc_t12"]
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path = sky130/sky130_osu_sc_t12
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url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12/
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README.md
34
README.md
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# riscv-wally
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# riscv-wally
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Configurable RISC-V Processor
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Configurable RISC-V Processor
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Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.
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To use Wally on Linux:
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```
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git clone https://github.com/davidharrishmc/riscv-wally
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cd riscv-wally
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cd imperas-riscv-tests
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make
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cd ../addins
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git clone https://github.com/riscv-non-isa/riscv-arch-test
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git clone https://github.com/riscv-software-src/riscv-isa-sim
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cd riscv-isa-sim
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mkdir build
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cd build
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set RISCV=/cad/riscv/gcc/bin (or whatever your path is)
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../configure --prefix=$RISCV
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make (this will take a while to build SPIKE)
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sudo make install
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cd ../../riscv-arch-test
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cp ../riscv-isa-sim/arch_test_target/spike/Makefile.include .
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edit Makefile.include
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change line with TARGETDIR to /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target (or whatever your path is)
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add line export RISCV_PREFIX = riscv64-unknown-elf- # this might not be needed if you have 32-bit versions of the riscv gcc compiler built separately
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make
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make XLEN=32
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exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim
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```
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Notes:
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Eventually download imperas-riscv-tests separately
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Move our custom tests to another directory
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Eventually replace exe2memfile.pl with objcopy
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