mirror of
https://github.com/openhwgroup/cvw
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
This commit is contained in:
David Harris
commit
eb7e5d4bc2
55
Makefile
55
Makefile
@ -44,7 +44,8 @@ imperasdv_cov:
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echo "0" > ${WALLY}/sim/seed0.txt
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb ${WALLY}/sim/cov/rv64gc_arch64i.ucdb --verbose
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/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
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run-elf-cov.bash --elf ${WALLY}/tests/output_folder/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
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vcover report -details -html sim/riscv.ucdb
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funcovreg:
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@ -56,6 +57,58 @@ funcovreg:
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iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover
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vcover report -details -html sim/riscv.ucdb
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# test_name=riscv_arithmetic_basic_test
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rvdv: sim/regression_logs sim/regression_ucdbs
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen >> sim/regression_logs/${test_name}.log 2>&1
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> sim/regression_logs/${test_name}.log 2>&1
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> sim/regression_logs/${test_name}.log 2>&1
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# run-elf.bash --seed ${WALLY}/sim/seed0.txt --verbose --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1
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/home/qabid/scripts/run-elf-cov.bash --seed ${WALLY}/sim/seed0.txt --verbose --coverdb sim/riscv.ucdb --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1
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cp sim/riscv.ucdb sim/regression_ucdbs/${test_name}.ucdb
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rvdv_regression:
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mkdir -p sim/regression_logs
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mkdir -p sim/regression_ucdbs
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cd sim/regression_logs && rm -rf *
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cd sim/regression_ucdbs && rm -rf *
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make rvdv test_name=riscv_arithmetic_basic_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_amo_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_ebreak_debug_mode_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_ebreak_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_arithmetic_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_mmu_stress_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_rand_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_full_interrupt_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_hint_instr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_illegal_instr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_invalid_csr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_jump_stress_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_loop_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_machine_mode_rand_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_mmu_stress_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_no_fence_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_non_compressed_instr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_pmp_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_privileged_mode_rand_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_rand_instr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_rand_jump_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_sfence_exception_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_unaligned_load_store_test >> sim/regression.log 2>&1
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rvdv_combine_coverage:
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mkdir -p sim/regcov
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cd sim/regcov && rm -rf *
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vcover merge sim/regcov/regcov.ucdb sim/regression_ucdbs/* -suppress 6854 -64
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vcover report -details -html sim/regcov/regcov.ucdb
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vcover report sim/regcov/regcov.ucdb -details -cvg > sim/regcov/regcov.ucdb.log
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vcover report sim/regcov/regcov.ucdb -testdetails -cvg > sim/regcov/regcov.ucdb.testdetails.log
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vcover report sim/regcov/regcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > sim/regcov/regcov.ucdb.summary.log
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grep "Total Coverage By Instance" sim/regcov/regcov.ucdb.log
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remove_rvdv_artifacts:
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rm sim/riscv.ucdb sim/regression.log covhtmlreport/ sim/regression_logs/ sim/regression_ucdbs/ sim/regcov/ -rf
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collect_riscvdv_regression_coverage: remove_rvdv_artifacts rvdv_regression rvdv_combine_coverage
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coverage:
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regression-wally -coverage -fp
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@ -53,6 +53,10 @@ Edit setup.sh and change the following lines to point to the path and license se
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export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
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export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa
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export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler
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export RISCV_TOOLCHAIN=/opt/riscv # Change this for your path to RISCV GNU toolchain
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export RISCV_GCC="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-gcc" # Copy this as it is
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export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-objcopy" # Copy this as it is
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export SPIKE_PATH=/usr/bin # Change this for your path to riscv-isa-sim (spike)
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If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.
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@ -40,8 +40,12 @@ vlog +incdir+../config/$1 \
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\
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+define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \
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+define+COVER_RV64I \
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+define+COVER_RV64C \
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+define+COVER_RV64M \
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+define+COVER_RV64A \
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+define+COVER_RV64F \
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+define+COVER_RV64D \
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+define+COVER_RV64ZICSR \
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+define+COVER_RV64C \
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+incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
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\
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