From b0aea77b2050855bff58b5300f4d71cfb3a508c9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 25 Aug 2022 10:35:24 -0500 Subject: [PATCH 1/6] Added generate around uncore. --- pipelined/regression/fpga-wave.do | 108 ++-- pipelined/regression/linux-wave.do | 42 +- pipelined/regression/wally-pipelined.do | 4 +- pipelined/regression/wave-all.do | 526 +++++++++--------- pipelined/regression/wave-dos/ahb-muldiv.do | 10 +- pipelined/regression/wave-dos/ahb-waves.do | 10 +- pipelined/regression/wave-dos/cache-waves.do | 6 +- .../regression/wave-dos/default-waves.do | 6 +- .../regression/wave-dos/peripheral-waves.do | 12 +- pipelined/regression/wave.do | 110 ++-- pipelined/src/wally/wallypipelinedsoc.sv | 18 +- pipelined/testbench/testbench-linux.sv | 16 +- pipelined/testbench/testbench.sv | 16 +- 13 files changed, 443 insertions(+), 441 deletions(-) diff --git a/pipelined/regression/fpga-wave.do b/pipelined/regression/fpga-wave.do index c0017fa3a..530698588 100644 --- a/pipelined/regression/fpga-wave.do +++ b/pipelined/regression/fpga-wave.do @@ -366,52 +366,52 @@ add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VI add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPending -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPriority -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intThreshold -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/nextIntPending -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/requests -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP -add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LSR -add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MCR -add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MSR -add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/RBR -add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/TXHR -add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LCR -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/INTR -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxstate -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txstate -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitssent -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitsexpected -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsreceived -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsexpected -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdata -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxshiftreg -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SOUTbit -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SINsync -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txsr -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SIN -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SOUT -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RTSb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DTRb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT1b -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT2b -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DSRb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DCDb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/CTSb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/TXRDYb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RXRDYb +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr +add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME +add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP +add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LSR +add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR +add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR +add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uncore/uart/uart/u/RBR +add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uncore/uart/uart/u/TXHR +add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LCR +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/INTR +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxstate +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txstate +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitssent +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitsexpected +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsreceived +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsexpected +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdata +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxshiftreg +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/SOUTbit +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/SINsync +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txsr +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SIN +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SOUT +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RTSb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DTRb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT1b +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT2b +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DSRb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DCDb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/CTSb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/TXRDYb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RXRDYb add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM @@ -461,14 +461,14 @@ add wave -noupdate -group sdc /testbench/dut/SDCCmdOut add wave -noupdate -group sdc /testbench/dut/SDCCmdOE add wave -noupdate -group sdc /testbench/dut/SDCDatIn add wave -noupdate -group sdc /testbench/dut/SDCCLK -add wave -noupdate -group sdc -color Gold -label {cmd fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/r_curr_state -add wave -noupdate -group sdc -color Gold -label {dat fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_dat_fsm/r_curr_state -add wave -noupdate -group sdc -color Gold -label {clk fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_clk_fsm/r_curr_state -add wave -noupdate -group sdc /testbench/dut/uncore/sdc/SDC/sd_top/slow_clk_divider/i_CLK -add wave -noupdate -group sdc /testbench/dut/uncore/sdc/SDC/sd_top/slow_clk_divider/o_CLK -add wave -noupdate -group sdc /testbench/dut/uncore/sdc/SDC/sd_top/slow_clk_divider/i_RST -add wave -noupdate -group sdc /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_TIMER_OUT -add wave -noupdate -group sdc /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/TIMER_OUT_GT_ZERO +add wave -noupdate -group sdc -color Gold -label {cmd fsm} /testbench/dut/uncore/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/r_curr_state +add wave -noupdate -group sdc -color Gold -label {dat fsm} /testbench/dut/uncore/uncore/sdc/SDC/sd_top/my_sd_dat_fsm/r_curr_state +add wave -noupdate -group sdc -color Gold -label {clk fsm} /testbench/dut/uncore/uncore/sdc/SDC/sd_top/my_clk_fsm/r_curr_state +add wave -noupdate -group sdc /testbench/dut/uncore/uncore/sdc/SDC/sd_top/slow_clk_divider/i_CLK +add wave -noupdate -group sdc /testbench/dut/uncore/uncore/sdc/SDC/sd_top/slow_clk_divider/o_CLK +add wave -noupdate -group sdc /testbench/dut/uncore/uncore/sdc/SDC/sd_top/slow_clk_divider/i_RST +add wave -noupdate -group sdc /testbench/dut/uncore/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_TIMER_OUT +add wave -noupdate -group sdc /testbench/dut/uncore/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/TIMER_OUT_GT_ZERO TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 5} {2668546 ns} 1} {{Cursor 2} {2003 ns} 1} {{Cursor 3} {16308899 ns} 0} quietly wave cursor active 3 diff --git a/pipelined/regression/linux-wave.do b/pipelined/regression/linux-wave.do index 007d9f2db..7bd2f01bb 100644 --- a/pipelined/regression/linux-wave.do +++ b/pipelined/regression/linux-wave.do @@ -420,27 +420,27 @@ add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PMAInstrAccessFaultF -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/SIN -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DSRb -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DCDb -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/CTSb -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/RIb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/SOUT -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RTSb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/DTRb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT1b -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT2b -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/INTR -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/TXRDYb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RXRDYb +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr +add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME +add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/SIN +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DSRb +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DCDb +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/CTSb +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/RIb +add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/SOUT +add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RTSb +add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/DTRb +add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT1b +add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT2b +add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/INTR +add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/TXRDYb +add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RXRDYb add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index 35c36322a..7f79cbfc5 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -57,7 +57,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" #run 100 ns #force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa - #force -deposit testbench/dut/uncore/clint/clint/MTIMECMP 64'h1000 + #force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000 run 14000 ms #add log -recursive /* #do linux-wave.do @@ -109,7 +109,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { #-- Run the Simulation # run 100 ns # force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa -# force -deposit testbench/dut/uncore/clint/clint/MTIMECMP 64'h1000 +# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000 # add log -recursive /* # do linux-wave.do # run -all diff --git a/pipelined/regression/wave-all.do b/pipelined/regression/wave-all.do index 5536313f9..2884c33b7 100644 --- a/pipelined/regression/wave-all.do +++ b/pipelined/regression/wave-all.do @@ -41,9 +41,9 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate /testbench/dut/core/ieu/dp/PCSrcE add wave -noupdate -divider add wave -noupdate /testbench/InstrMName -add wave -noupdate /testbench/dut/uncore/ram/memwrite -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWDATA +add wave -noupdate /testbench/dut/uncore/uncore/ram/memwrite +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HADDR +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWDATA add wave -noupdate -divider add wave -noupdate -radix hexadecimal /testbench/PCW add wave -noupdate /testbench/InstrWName @@ -1295,266 +1295,266 @@ add wave -noupdate -radix hexadecimal /testbench/dut/imem/InstrAccessFaultF add wave -noupdate -radix hexadecimal /testbench/dut/imem/adrbits add wave -noupdate -radix hexadecimal /testbench/dut/imem/rd add wave -noupdate -radix hexadecimal /testbench/dut/imem/rd2 -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HCLK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESETn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWDATAIN -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWRITE -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HSIZE -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HBURST -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HPROT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HTRANS -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HMASTLOCK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRDATAEXT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADYEXT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESPEXT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRDATA -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADY -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESP -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/DataAccessFaultM -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/TimerIntM -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/SwIntM -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/GPIOPinsIn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/GPIOPinsOut -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/GPIOPinsEn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/UARTSin -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/UARTSout -add wave -noupdate -radix hexadecimal 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-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/MemRWtim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HWDATA -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HSELTim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HREADTim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HRESPTim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HREADYTim -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/entry -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/memread -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/memwrite -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/busycount -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HCLK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HRESETn -add wave -noupdate -radix hexadecimal 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/testbench/dut/uncore/gpio/INPUT_EN -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/OUTPUT_EN -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/OUTPUT_VAL -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/entry -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/memread -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/memwrite -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HCLK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HRESETn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/MemRWuart -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HADDR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HWDATA -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HREADUART -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HRESPUART -add wave -noupdate -radix hexadecimal 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hexadecimal /testbench/dut/uncore/uart/A -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/MEMRb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/MEMWb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/Din -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/Dout -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/BAUDOUTb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/HCLK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/HRESETn -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/A -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/Din -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/Dout -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/MEMRb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/MEMWb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/INTR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/TXRDYb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RXRDYb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/BAUDOUTb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RCLK -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SIN -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DSRb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DCDb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/CTSb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RIb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SOUT -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RTSb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DTRb -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/OUT1b -add wave -noupdate -radix hexadecimal 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-radix hexadecimal /testbench/dut/uncore/uart/u/CTSbd -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RIbd -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SINsync -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DSRbsync -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DCDbsync -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/CTSbsync -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RIbsync -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DSRb2 -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DCDb2 -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/CTSb2 -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RIb2 -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SOUTbit -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/loop -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DLAB -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/baudpulse -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txbaudpulse -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxbaudpulse -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/baudcount -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxoversampledcnt -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txoversampledcnt -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxbitsreceived -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txbitssent -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxstate -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txstate -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxshiftreg -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifohead -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifotail -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifohead -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifotail -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifotriggerlevel -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifoentries -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifoentries -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxbitsexpected -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txbitsexpected -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RXBR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxtimeoutcnt -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxcentered -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxparity -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxparitybit -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxstopbit -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxparityerr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxoverrunerr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxframingerr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxbreak -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifohaserr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxdataready -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifoempty -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifotriggered -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifotimeout -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifodmaready -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxdata9 -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxdata -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxerrbit -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfullbit -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/TXHR -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txdata -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/nexttxdata -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txsr -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txnextbit -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txhrfull -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txsrfull -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txparity -add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifoempty -add wave -noupdate -radix hexadecimal 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/testbench/dut/uncore/uncore/uart/u/DLAB +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/baudpulse +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbaudpulse +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbaudpulse +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/baudcount +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxoversampledcnt +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txoversampledcnt +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbitsreceived +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbitssent +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxstate +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txstate +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxshiftreg +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifohead +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotail +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifohead +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifotail +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotriggerlevel +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifoentries +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifoentries +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbitsexpected +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbitsexpected +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RXBR +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxtimeoutcnt +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxcentered +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparity +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparitybit +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxstopbit +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparityerr +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxoverrunerr +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxframingerr +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbreak +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifohaserr +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdataready +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifoempty +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotriggered +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotimeout +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifodmaready +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdata9 +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdata +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxerrbit +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfullbit +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/TXHR +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txdata +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/nexttxdata +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txsr +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txnextbit +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txhrfull +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txsrfull +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txparity +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifoempty +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifofull +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifodmaready +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/fifoenabled +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/fifodmamodesel +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/evenparitysel +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxlinestatusintr +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdataavailintr +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txhremptyintr +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/modemstatusintr +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/intrpending +add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/intrid add wave -noupdate -radix hexadecimal /testbench/it/clk add wave -noupdate -radix hexadecimal /testbench/it/reset add wave -noupdate -radix hexadecimal /testbench/it/FlushE diff --git a/pipelined/regression/wave-dos/ahb-muldiv.do b/pipelined/regression/wave-dos/ahb-muldiv.do index af7de3800..3170bc969 100644 --- a/pipelined/regression/wave-dos/ahb-muldiv.do +++ b/pipelined/regression/wave-dos/ahb-muldiv.do @@ -52,9 +52,9 @@ add wave -divider add wave -hex /testbench/dut/core/ifu/PCM add wave -hex /testbench/dut/core/ifu/InstrM add wave /testbench/InstrMName -add wave /testbench/dut/uncore/ram/memwrite -add wave -hex /testbench/dut/uncore/HADDR -add wave -hex /testbench/dut/uncore/HWDATA +add wave /testbench/dut/uncore/uncore/ram/memwrite +add wave -hex /testbench/dut/uncore/uncore/HADDR +add wave -hex /testbench/dut/uncore/uncore/HWDATA add wave -divider add wave -hex /testbench/dut/core/ebu/ebu/MemReadM @@ -71,7 +71,7 @@ add wave -hex /testbench/dut/core/ebu/ebu/HBURST add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM add wave -divider -add wave -hex /testbench/dut/uncore/ram/* +add wave -hex /testbench/dut/uncore/uncore/ram/* add wave -divider add wave -hex /testbench/dut/core/ifu/PCW @@ -83,7 +83,7 @@ add wave -hex /testbench/dut/core/ieu/dp/ResultW add wave -hex /testbench/dut/core/ieu/dp/RdW add wave -divider -add wave -hex /testbench/dut/uncore/ram/* +add wave -hex /testbench/dut/uncore/uncore/ram/* add wave -divider # appearance diff --git a/pipelined/regression/wave-dos/ahb-waves.do b/pipelined/regression/wave-dos/ahb-waves.do index f084f71fc..37a397d04 100644 --- a/pipelined/regression/wave-dos/ahb-waves.do +++ b/pipelined/regression/wave-dos/ahb-waves.do @@ -40,9 +40,9 @@ add wave -divider add wave -hex /testbench/dut/core/ifu/PCM add wave -hex /testbench/dut/core/ifu/InstrM add wave /testbench/InstrMName -add wave /testbench/dut/uncore/ram/memwrite -add wave -hex /testbench/dut/uncore/HADDR -add wave -hex /testbench/dut/uncore/HWDATA +add wave /testbench/dut/uncore/uncore/ram/memwrite +add wave -hex /testbench/dut/uncore/uncore/HADDR +add wave -hex /testbench/dut/uncore/uncore/HWDATA add wave -divider add wave -hex /testbench/dut/core/ebu/ebu/MemReadM @@ -58,7 +58,7 @@ add wave -hex /testbench/dut/core/ebu/ebu/HWDATA add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM add wave -divider -add wave -hex /testbench/dut/uncore/ram/* +add wave -hex /testbench/dut/uncore/uncore/ram/* add wave -divider add wave -hex /testbench/dut/core/ifu/PCW @@ -70,7 +70,7 @@ add wave -hex /testbench/dut/core/ieu/dp/ResultW add wave -hex /testbench/dut/core/ieu/dp/RdW add wave -divider -add wave -hex /testbench/dut/uncore/ram/* +add wave -hex /testbench/dut/uncore/uncore/ram/* add wave -divider add wave -hex -r /testbench/* diff --git a/pipelined/regression/wave-dos/cache-waves.do b/pipelined/regression/wave-dos/cache-waves.do index 6e5e3ad45..ff6e855ec 100644 --- a/pipelined/regression/wave-dos/cache-waves.do +++ b/pipelined/regression/wave-dos/cache-waves.do @@ -36,9 +36,9 @@ add wave -divider add wave -hex /testbench/dut/core/ifu/PCM add wave -hex /testbench/dut/core/ifu/InstrM add wave /testbench/InstrMName -add wave /testbench/dut/uncore/ram/memwrite -add wave -hex /testbench/dut/uncore/HADDR -add wave -hex /testbench/dut/uncore/HWDATA +add wave /testbench/dut/uncore/uncore/ram/memwrite +add wave -hex /testbench/dut/uncore/uncore/HADDR +add wave -hex /testbench/dut/uncore/uncore/HWDATA add wave -divider add wave -hex /testbench/dut/core/ebu/ebu/MemReadM diff --git a/pipelined/regression/wave-dos/default-waves.do b/pipelined/regression/wave-dos/default-waves.do index 92cd30f16..2c7f0f755 100644 --- a/pipelined/regression/wave-dos/default-waves.do +++ b/pipelined/regression/wave-dos/default-waves.do @@ -37,9 +37,9 @@ add wave -divider add wave -hex /testbench/dut/core/ifu/PCM add wave -hex /testbench/dut/core/ifu/InstrM add wave /testbench/InstrMName -add wave /testbench/dut/uncore/ram/memwrite -add wave -hex /testbench/dut/uncore/HADDR -add wave -hex /testbench/dut/uncore/HWDATA +add wave /testbench/dut/uncore/uncore/ram/memwrite +add wave -hex /testbench/dut/uncore/uncore/HADDR +add wave -hex /testbench/dut/uncore/uncore/HWDATA add wave -divider add wave -hex /testbench/PCW add wave -hex /testbench/InstrW diff --git a/pipelined/regression/wave-dos/peripheral-waves.do b/pipelined/regression/wave-dos/peripheral-waves.do index 7ee4e2b56..3f3974dc2 100644 --- a/pipelined/regression/wave-dos/peripheral-waves.do +++ b/pipelined/regression/wave-dos/peripheral-waves.do @@ -45,7 +45,7 @@ add wave -hex /testbench/dut/core/ifu/PCM add wave -hex /testbench/dut/core/ifu/InstrM add wave -hex /testbench/dut/core/ieu/c/InstrValidM add wave /testbench/InstrMName -add wave /testbench/dut/uncore/ram/memwrite +add wave /testbench/dut/uncore/uncore/ram/memwrite add wave -hex /testbench/dut/core/WriteDataM add wave -hex /testbench/dut/core/lsu.bus.dcache/MemPAdrM add wave -hex /testbench/dut/core/lsu.bus.dcache/WriteDataM @@ -102,13 +102,13 @@ add wave -hex /testbench/dut/core/ieu/dp/regf/rf[31] # peripherals add wave -divider PLIC add wave -hex /testbench/dut/core/priv/csr/TrapM -add wave -hex /testbench/dut/uncore/plic/plic/* -add wave -hex /testbench/dut/uncore/plic/plic/intPriority -add wave -hex /testbench/dut/uncore/plic/plic/pendingArray +add wave -hex /testbench/dut/uncore/uncore/plic/plic/* +add wave -hex /testbench/dut/uncore/uncore/plic/plic/intPriority +add wave -hex /testbench/dut/uncore/uncore/plic/plic/pendingArray add wave -divider UART -add wave -hex /testbench/dut/uncore/uart/uart/u/* +add wave -hex /testbench/dut/uncore/uncore/uart/uart/u/* add wave -divider GPIO -add wave -hex /testbench/dut/uncore/gpio/gpio/* +add wave -hex /testbench/dut/uncore/uncore/gpio/gpio/* #add wave -divider #add wave -hex /testbench/dut/core/ebu/ebu/* #add wave -divider diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index d992ee664..bb22b1576 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -361,61 +361,61 @@ add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VI add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPending -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPriority -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intThreshold -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/nextIntPending -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/requests -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/irqMatrix -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/priorities_with_irqs -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/max_priority_with_irqs -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/irqs_at_max_priority -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP -add wave -noupdate -group uart -expand -group Registers -expand /testbench/dut/uncore/uart/uart/u/LSR -add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MCR -add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MSR -add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/RBR -add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/TXHR -add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/LCR -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/INTR -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxstate -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txstate -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitssent -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitsexpected -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsreceived -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsexpected -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdata -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxoverrunerr -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdataready -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdataavailintr -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/RXBR -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/squashRXerrIP -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxshiftreg -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SOUTbit -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SINsync -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txsr -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SIN -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SOUT -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RTSb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DTRb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT1b -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT2b -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DSRb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DCDb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/CTSb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/TXRDYb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RXRDYb +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqMatrix +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/priorities_with_irqs +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr +add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME +add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP +add wave -noupdate -group uart -expand -group Registers -expand /testbench/dut/uncore/uncore/uart/uart/u/LSR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/RBR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/TXHR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LCR +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/INTR +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxstate +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txstate +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitssent +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitsexpected +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsreceived +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsexpected +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdata +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxoverrunerr +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataready +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataavailintr +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/RXBR +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/squashRXerrIP +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxshiftreg +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/SOUTbit +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/SINsync +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txsr +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SIN +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SOUT +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RTSb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DTRb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT1b +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT2b +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DSRb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DCDb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/CTSb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/TXRDYb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RXRDYb add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index ff1d95005..e1b642494 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -93,12 +93,14 @@ module wallypipelinedsoc ( .HADDRD, .HSIZED, .HWRITED ); - uncore uncore(.HCLK, .HRESETn, .TIMECLK, - .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, - .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HWRITED, - .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, - .HSELEXT, - .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK - -); + if (`DBUS | `IBUS) begin : uncore + uncore uncore(.HCLK, .HRESETn, .TIMECLK, + .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, + .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HWRITED, .HSELEXT, + .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, + .UARTSout, .MTIME_CLINT, + .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK + ); + end + endmodule diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index cf6a6d394..6b8a39cf2 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -175,13 +175,13 @@ module testbench; `define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE `define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE `define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE - `define UART dut.uncore.uart.uart.u + `define UART dut.uncore.uncore.uart.uart.u `define UART_IER `UART.IER `define UART_LCR `UART.LCR `define UART_MCR `UART.MCR `define UART_SCR `UART.SCR `define UART_IP `UART.INTR - `define PLIC dut.uncore.plic.plic + `define PLIC dut.uncore.uncore.plic.plic `define PLIC_INT_PRIORITY `PLIC.intPriority `define PLIC_INT_ENABLE `PLIC.intEn `define PLIC_THRESHOLD `PLIC.intThreshold @@ -422,14 +422,14 @@ module testbench; ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"}; // initialize bootrom memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb"); - readResult = $fread(dut.uncore.bootrom.bootrom.memory.ROM,memFile); + readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM,memFile); $fclose(memFile); // initialize RAM and ROM if (CHECKPOINT==0) memFile = $fopen({testvectorDir,"ram.bin"}, "rb"); else memFile = $fopen({checkpointDir,"ram.bin"}, "rb"); - readResult = $fread(dut.uncore.ram.ram.memory.RAM,memFile); + readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM,memFile); $fclose(memFile); // ---------- Ground-Zero ----------- if (CHECKPOINT==0) begin @@ -441,7 +441,7 @@ module testbench; AttemptedInstructionCount = 1; // offset needed here when running from ground zero // ---------- Checkpoint ---------- end else begin - //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.memory.RAM); + //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.uncore.ram.ram.memory.RAM); traceFileE = $fopen({checkpointDir,"all.txt"}, "r"); traceFileM = $fopen({checkpointDir,"all.txt"}, "r"); interruptFile = $fopen({testvectorDir,"interrupts.txt"}, "r"); @@ -568,7 +568,7 @@ module testbench; if(textM.substr(0,5) == "rdtime") begin \ //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \ if(!NO_SPOOFING) \ - force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \ + force dut.uncore.uncore.clint.clint.MTIME = ExpectedRegValueM; \ end \ end \ end \ @@ -645,7 +645,7 @@ module testbench; if(textW.substr(0,5) == "rdtime") begin //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount); if(!NO_SPOOFING) - release dut.uncore.clint.clint.MTIME; + release dut.uncore.uncore.clint.clint.MTIME; end //if (ExpectedIEUAdrM == 'h10000005) begin //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, AttemptedInstructionCount); @@ -840,7 +840,7 @@ module testbench; PAdr = BaseAdr + (VPN[i] << 3); // ram.memory.RAM is 64-bit addressed. PAdr specifies a byte. We right shift // by 3 (the PTE size) to get the requested 64-bit PTE. - PTE = dut.uncore.ram.ram.memory.RAM[PAdr >> 3]; + PTE = dut.uncore.uncore.ram.ram.memory.RAM[PAdr >> 3]; PTE_R = PTE[1]; PTE_X = PTE[3]; if (PTE_R | PTE_X) begin diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 6f273accb..a423a6995 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -214,7 +214,7 @@ logic [3:0] dummy; // the design. if (TEST == "coremark") for (i=MemStartAddr; i Date: Thu, 25 Aug 2022 11:02:46 -0500 Subject: [PATCH 2/6] BROKEN. Don't use this commit. Issue running cacheless with bus. --- pipelined/config/buildroot/wally-config.vh | 3 +-- pipelined/config/fpga/wally-config.vh | 3 +-- pipelined/config/rv32e/wally-config.vh | 3 +-- pipelined/config/rv32gc/wally-config.vh | 3 +-- pipelined/config/rv32i/wally-config.vh | 3 +-- pipelined/config/rv32ic/wally-config.vh | 3 +-- pipelined/config/rv64BP/wally-config.vh | 3 +-- pipelined/config/rv64fp/wally-config.vh | 3 +-- pipelined/config/rv64fpquad/wally-config.vh | 3 +-- pipelined/config/rv64gc/wally-config.vh | 3 +-- pipelined/config/rv64i/wally-config.vh | 3 +-- pipelined/config/rv64ic/wally-config.vh | 3 +-- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/lsu.sv | 2 +- pipelined/src/wally/wallypipelinedcore.sv | 2 +- pipelined/src/wally/wallypipelinedsoc.sv | 2 +- pipelined/testbench/testbench.sv | 6 +++--- 17 files changed, 19 insertions(+), 31 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 1488e528a..cb6658b1c 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -51,8 +51,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 58e425b3b..76b587924 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -53,8 +53,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 19098a0a1..352554006 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -52,8 +52,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 6c2bdd31e..47991e014 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -51,8 +51,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index c785841d0..78b85286a 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -52,8 +52,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 1cdd10d59..27e4db2ef 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -51,8 +51,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 0 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index f2ca2420e..8af61d884 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -53,8 +53,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index 4c7c57ed4..653dd864e 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -54,8 +54,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index f1806e0e6..6a40a6885 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -53,8 +53,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 5696252f8..eef5448b4 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -53,8 +53,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index ea3f74d40..c0477fc62 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -53,8 +53,7 @@ // LSU microarchitectural Features `define DMEM 0 `define IROM 0 -`define DBUS 1 -`define IBUS 1 +`define BUS 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index 7b3d35234..ddd68f9dc 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -53,8 +53,7 @@ // LSU microarchitectural Features `define DMEM 1 `define IROM 1 -`define DBUS 1 -`define IBUS 1 +`define BUS 0 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index c1ac1b8f1..59cdb7b88 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -192,7 +192,7 @@ module ifu ( assign {BusStall, IFUBusRead} = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; end - if (`IBUS) begin : bus + if (`BUS) begin : bus localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN; localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 1b7804d8e..9c68ee17d 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -210,7 +210,7 @@ module lsu ( assign {DCacheStallM, DCacheCommittedM} = '0; assign {DCacheMiss, DCacheAccess} = '0; end - if (`DBUS) begin : bus + if (`BUS) begin : bus localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN; localparam integer LOGBWPL = `DCACHE ? $clog2(WORDSPERLINE) : 1; diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index e620231aa..508b775dc 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -292,7 +292,7 @@ module wallypipelinedcore ( // *** Ross: please make EBU conditional when only supporting internal memories - if(`DBUS | `IBUS) begin : ebu + if(`BUS) begin : ebu ahblite ebu(// IFU connections .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index e1b642494..b62ee2835 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -93,7 +93,7 @@ module wallypipelinedsoc ( .HADDRD, .HSIZED, .HWRITED ); - if (`DBUS | `IBUS) begin : uncore + if (`BUS) begin : uncore uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HWRITED, .HSELEXT, diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index a423a6995..f7b71288f 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -233,7 +233,7 @@ logic [3:0] dummy; force dut.uncore.uncore.sdc.SDC.LimitTimers = 1; end else begin if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); - else $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); end @@ -459,8 +459,8 @@ module riscvassertions; // assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - //assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS."); - //assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS."); + //assert (`DCACHE == 1 & `BUS ==0) else $error("Dcache requires DBUS."); + //assert (`ICACHE == 1 & `BUS ==0) else $error("Icache requires IBUS."); assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); end From 3b612d62011bc3e0f787f351ce6b0d03a33bd9c9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 25 Aug 2022 14:42:08 -0500 Subject: [PATCH 3/6] Possible fixes for earily messup of rv32ic and rv64ic configs. --- pipelined/config/rv32ic/wally-config.vh | 8 ++++---- pipelined/regression/wally-pipelined-batch.do | 2 +- pipelined/testbench/testbench.sv | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 27e4db2ef..2f08e2f28 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -49,11 +49,11 @@ `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 // LSU microarchitectural Features -`define DMEM 0 -`define IROM 0 +`define DMEM 1 +`define IROM 1 `define BUS 0 -`define DCACHE 1 -`define ICACHE 1 +`define DCACHE 0 +`define ICACHE 0 `define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 diff --git a/pipelined/regression/wally-pipelined-batch.do b/pipelined/regression/wally-pipelined-batch.do index 698ba4a37..eed0295bc 100644 --- a/pipelined/regression/wally-pipelined-batch.do +++ b/pipelined/regression/wally-pipelined-batch.do @@ -56,7 +56,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { exec ./slack-notifier/slack-notifier.py } else { - vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 + vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index f7b71288f..e05694c2d 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -223,7 +223,7 @@ logic [3:0] dummy; else pathname = tvpaths[1]; */ if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; else memfilename = {pathname, tests[test], ".elf.memfile"}; - if (TEST == "fpga") begin + if (`FPGA) begin string romfilename, sdcfilename; romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; From 179aec3616e3bb5ca4abc60f1f9b447e4c1a3a80 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 25 Aug 2022 15:03:54 -0500 Subject: [PATCH 4/6] Still not working with rv32ic. --- pipelined/src/ifu/irom.sv | 2 +- pipelined/testbench/testbench.sv | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv index 83585c07e..2670511e1 100644 --- a/pipelined/src/ifu/irom.sv +++ b/pipelined/src/ifu/irom.sv @@ -40,7 +40,7 @@ module irom( localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size localparam OFFSET = $clog2(`LLEN/8); - brom1p1rw #(ADDR_WDITH, 32) + brom1p1r #(ADDR_WDITH, 32) rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData)); endmodule diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index e05694c2d..7413a4c00 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -232,9 +232,9 @@ logic [3:0] dummy; // force sdc timers force dut.uncore.uncore.sdc.SDC.LimitTimers = 1; end else begin - if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); + if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); + if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); end if (riscofTest) begin @@ -328,7 +328,7 @@ logic [3:0] dummy; /* verilator lint_off INFINITELOOP */ while (signature[i] !== 'bx) begin logic [`XLEN-1:0] sig; - if (`DMEM) sig = dut.core.lsu.dtim.dtim.ram.memory.RAM[testadrNoBase+i]; + if (`DMEM) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin @@ -361,9 +361,9 @@ logic [3:0] dummy; if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; else memfilename = {pathname, tests[test], ".elf.memfile"}; //$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); + if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); + if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); if (riscofTest) begin ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; From 5c2bc20dbdc90595376666e85cb1079cb3a1925e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 25 Aug 2022 15:52:25 -0500 Subject: [PATCH 5/6] Almost fixed issues with irom and dtim address selection. --- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/lsu.sv | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index b5ce73c41..1e82cad3f 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -185,7 +185,7 @@ module ifu ( assign InstrRawF = AllInstrRawF[31:0]; if (`IROM) begin : irom - irom irom(.clk, .reset, .Adr(PCNextFSpill), .ReadData(FinalInstrRawF)); + irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCPF : PCNextFSpill), .ReadData(FinalInstrRawF)); assign {BusStall, IFUBusRead} = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 416e62a18..107afcf42 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -201,7 +201,9 @@ module lsu ( // *** becomes DTIM_RAM_BASE if (`DMEM) begin : dtim - dtim dtim(.clk, .reset, .LSURWM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), + dtim dtim(.clk, .reset, .LSURWM, + .IEUAdrE(CPUBusy | LSURWM[0] | reset ? IEUAdrM : IEUAdrE), + .TrapM, .WriteDataM(LSUWriteDataM), .ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM)); // since we have a local memory the bus connections are all disabled. From 8c8b95ecf55dfdc170b50528a02f3097e5b1482d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 25 Aug 2022 16:00:55 -0500 Subject: [PATCH 6/6] Finally resolved the issues with the rv32ic and rv64ic configurations. --- pipelined/src/ifu/ifu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 1e82cad3f..4577b4206 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -185,7 +185,7 @@ module ifu ( assign InstrRawF = AllInstrRawF[31:0]; if (`IROM) begin : irom - irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCPF : PCNextFSpill), .ReadData(FinalInstrRawF)); + irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCFSpill : PCNextFSpill), .ReadData(FinalInstrRawF)); assign {BusStall, IFUBusRead} = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;