mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Use macro for CSR connections in wallyTracer
This commit is contained in:
Jordan Carlin
parent
fd82aa2e5b
commit
eb38d07568
@ -29,6 +29,18 @@
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`define PRINT_ALL 0
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`define PRINT_CSRS 0
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// Since we are detecting the CSR change by comparing the old value, we need to
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// ensure the CSR is detected when the pipeline's Writeback stage is not
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// stalled. If it is stalled we want CSRArray to hold the old value.
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`define CONNECT_CSR(addr, val) \
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always_comb \
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if (valid) CSRArray[addr] = val; \
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else CSRArray[addr] = CSRArrayOld[addr]; \
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always_ff @(posedge clk) \
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CSRArrayOld[addr] = CSRArray[addr]; \
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assign CSR_W[addr] = (CSRArrayOld[addr] != CSRArray[addr]) ? 1 : 0; \
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assign rvvi.csr_wb[0][0][addr] = CSR_W[addr]; \
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assign rvvi.csr[0][0][addr] = CSRArray[addr];
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module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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@ -65,6 +77,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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logic [11:0] CSRAdrM, CSRAdrW;
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logic wfiM;
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logic InterruptM, InterruptW;
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logic valid;
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//For VM Verification
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logic [(P.XLEN-1):0] IVAdrF,IVAdrD,IVAdrE,IVAdrM,IVAdrW,DVAdrM,DVAdrW;
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@ -129,32 +142,97 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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assign IPageTypeF = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
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assign DPageTypeM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
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logic valid;
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// CSR connections
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if (P.ZICSR_SUPPORTED) begin
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// M-mode trap CSRs
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`CONNECT_CSR(12'h300, testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW);
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`CONNECT_CSR(12'h302, testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW);
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`CONNECT_CSR(12'h303, testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
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`CONNECT_CSR(12'h304, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW);
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`CONNECT_CSR(12'h305, testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW);
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`CONNECT_CSR(12'h340, testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW);
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`CONNECT_CSR(12'h341, testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW);
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`CONNECT_CSR(12'h342, testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW);
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`CONNECT_CSR(12'h343, testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW);
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`CONNECT_CSR(12'h344, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW);
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// S-mode trap CSRs
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`CONNECT_CSR(12'h100, testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW);
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`CONNECT_CSR(12'h104, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222);
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`CONNECT_CSR(12'h105, testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW);
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`CONNECT_CSR(12'h140, testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW);
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`CONNECT_CSR(12'h141, testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW);
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`CONNECT_CSR(12'h142, testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW);
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`CONNECT_CSR(12'h143, testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW);
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`CONNECT_CSR(12'h144, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
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// Virtual Memory CSRs
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`CONNECT_CSR(12'h180, testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW);
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// Floating-Point CSRs
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`CONNECT_CSR(12'h001, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW);
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`CONNECT_CSR(12'h002, testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW);
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`CONNECT_CSR(12'h003, {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW});
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// Counters / Performance Monitoring CSRs
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`CONNECT_CSR(12'h306, testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW);
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`CONNECT_CSR(12'h106, testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW);
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`CONNECT_CSR(12'h320, testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW);
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// mhpmevent3-31 not connected (232-33F)
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`CONNECT_CSR(12'hB00, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]); // MCYCLE
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`CONNECT_CSR(12'hB02, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]); // MINSTRET
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// mhpmcounter3-31 not connected (B03-B1F)
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// cycle, time, instret not connected (C00-C02)
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// hpmcounter3-31 not connected (C03-C1F)
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// Machine Information Registers and Configuration CSRs
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`CONNECT_CSR(12'h301, testbench.dut.core.priv.priv.csr.csrm.MISA_REGW);
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`CONNECT_CSR(12'h30A, testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW);
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`CONNECT_CSR(12'h10A, testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW);
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`CONNECT_CSR(12'h747, 0); // mseccfg
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`CONNECT_CSR(12'hF11, 0); //mvendorid
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`CONNECT_CSR(12'hF12, 0); // marchid
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`CONNECT_CSR(12'hF13, {{P.XLEN-12{1'b0}}, 12'h100}); // mimpid
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`CONNECT_CSR(12'hF14, testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW);
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`CONNECT_CSR(12'hF15, 0); //mconfigptr
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// Sstc CSRs
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`CONNECT_CSR(12'h14D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0]);
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// Zkr CSRs
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// seed not connected (015)
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// extra CSRs for RV32
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if (P.XLEN == 32) begin
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`CONNECT_CSR(12'h310, testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW);
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`CONNECT_CSR(12'h31A, testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW);
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`CONNECT_CSR(12'h757, 0); // mseccfgh
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`CONNECT_CSR(12'h15D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32]);
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end
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end
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// PMP CSRs
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if (P.PMP_ENTRIES > 0) begin
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always_comb begin
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// Since we are detected the CSR change by comparing the old value we need to
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// ensure the CSR is detected when the pipeline's Writeback stage is not
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// stalled. If it is stalled we want CSRArray to hold the old value.
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if(valid) begin
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// PMPCFG CSRs (space is 0-15 3a0 - 3af)
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localparam inc = P.XLEN == 32 ? 4 : 8;
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int i, i4, i8, csrid;
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int i, i4, csrid;
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logic [P.XLEN-1:0] pmp;
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for (i=0; i<P.PMP_ENTRIES; i+=inc) begin
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i4 = i / 4;
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i8 = (i / inc) * inc;
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csrid = 12'h3A0 + i4;
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pmp = 0;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+0] << 0;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+1] << 8;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+2] << 16;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+3] << 24;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+4] << 32;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+5] << 40;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+6] << 48;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+7] << 56;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+0] << 0;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+1] << 8;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+2] << 16;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+3] << 24;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+4] << 32;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+5] << 40;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+6] << 48;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+7] << 56;
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CSRArray[csrid] = pmp;
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end
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@ -166,71 +244,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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CSRArray[csrid] = pmp;
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end
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// M-mode trap CSRs
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CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
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CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW;
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CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
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CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
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CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
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CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
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CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW;
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CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
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CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
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CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
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// S-mode trap CSRs
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CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW;
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CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222;
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CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
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CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
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CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
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CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
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CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
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CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
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// Virtual Memory CSRs
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CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
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// Floating-Point CSRs
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CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
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CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
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CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW};
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// Counters / Performance Monitoring CSRs
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CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW;
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CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
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CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW;
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// mhpmevent3-31 not connected (232-33F)
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CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; // MCYCLE
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CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; // MINSTRET
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// mhpmcounter3-31 not connected (B03-B1F)
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// cycle, time, instret not connected (C00-C02)
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// hpmcounter3-31 not connected (C03-C1F)
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// Machine Information Registers and Configuration CSRs
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CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
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CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
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CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
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CSRArray[12'h747] = 0; // mseccfg
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CSRArray[12'hF11] = 0; //mvendorid
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CSRArray[12'hF12] = 0; // marchid
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CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; // mimpid
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CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
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CSRArray[12'hF15] = 0; //mconfigptr
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// Sstc CSRs
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CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0];
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// Zkr CSRs
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// seed not connected (015)
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// extra CSRs for RV32
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if (P.XLEN == 32) begin
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CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW;
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CSRArray[12'h31A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW;
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CSRArray[12'h757] = 0; // mseccfgh
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CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32];
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end
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end else begin // hold the old value if the pipeline is stalled.
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// PMP CFG 3A0 to 3AF
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int csrid;
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@ -240,79 +253,37 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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// PMP ADDR 3B0 to 3EF
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for(csrid='h3B0; csrid<='h3EF; csrid++)
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CSRArray[csrid] = CSRArrayOld[csrid];
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// M-mode trap CSRs
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CSRArray[12'h300] = CSRArrayOld[12'h300];
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CSRArray[12'h302] = CSRArrayOld[12'h302];
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CSRArray[12'h303] = CSRArrayOld[12'h303];
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CSRArray[12'h304] = CSRArrayOld[12'h304];
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CSRArray[12'h305] = CSRArrayOld[12'h305];
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CSRArray[12'h340] = CSRArrayOld[12'h340];
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CSRArray[12'h341] = CSRArrayOld[12'h341];
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CSRArray[12'h342] = CSRArrayOld[12'h342];
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CSRArray[12'h343] = CSRArrayOld[12'h343];
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CSRArray[12'h344] = CSRArrayOld[12'h344];
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// S-mode trap CSRs
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CSRArray[12'h100] = CSRArrayOld[12'h100];
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CSRArray[12'h104] = CSRArrayOld[12'h104];
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CSRArray[12'h105] = CSRArrayOld[12'h105];
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CSRArray[12'h140] = CSRArrayOld[12'h140];
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CSRArray[12'h141] = CSRArrayOld[12'h141];
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CSRArray[12'h142] = CSRArrayOld[12'h142];
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CSRArray[12'h143] = CSRArrayOld[12'h143];
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CSRArray[12'h144] = CSRArrayOld[12'h144];
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// Virtual Memory CSRs
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CSRArray[12'h180] = CSRArrayOld[12'h180] ;
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// Floating-Point CSRs
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CSRArray[12'h001] = CSRArrayOld[12'h001];
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CSRArray[12'h002] = CSRArrayOld[12'h002];
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CSRArray[12'h003] = CSRArrayOld[12'h003];
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// Counters / Performance Monitoring CSRs
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CSRArray[12'h306] = CSRArrayOld[12'h306];
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CSRArray[12'h106] = CSRArrayOld[12'h106];
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CSRArray[12'h320] = CSRArrayOld[12'h320];
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// mhpmevent3-31 not connected (232-33F)
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CSRArray[12'hB00] = CSRArrayOld[12'hB00];
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CSRArray[12'hB02] = CSRArrayOld[12'hB02];
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// mhpmcounter3-31 not connected (B03-B1F)
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// cycle, time, instret not connected (C00-C02)
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// hpmcounter3-31 not connected (C03-C1F)
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// Machine Information Registers and Configuration CSRs
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CSRArray[12'h301] = CSRArrayOld[12'h301];
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CSRArray[12'h30A] = CSRArrayOld[12'h30A];
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CSRArray[12'h10A] = CSRArrayOld[12'h10A];
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CSRArray[12'h747] = CSRArrayOld[12'h747];
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CSRArray[12'hF11] = CSRArrayOld[12'hF11];
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CSRArray[12'hF12] = CSRArrayOld[12'hF12];
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CSRArray[12'hF13] = CSRArrayOld[12'hF13];
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CSRArray[12'hF14] = CSRArrayOld[12'hF14];
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CSRArray[12'hF15] = CSRArrayOld[12'hF15];
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// Sstc CSRs
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CSRArray[12'h14D] = CSRArrayOld[12'h14D];
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||||
// Zkr CSRs
|
||||
// seed not connected (015)
|
||||
|
||||
// extra CSRs for RV32
|
||||
if (P.XLEN == 32) begin
|
||||
CSRArray[12'h310] = CSRArrayOld[12'h310];
|
||||
CSRArray[12'h31A] = CSRArrayOld[12'h31A];
|
||||
CSRArray[12'h757] = CSRArrayOld[12'h757];
|
||||
CSRArray[12'h15D] = CSRArrayOld[12'h15D];
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
// no CSRArray
|
||||
end
|
||||
|
||||
// record previous csr value.
|
||||
always_ff @(posedge clk) begin
|
||||
int csrid;
|
||||
// PMP CFG 3A0 to 3AF
|
||||
for(csrid='h3A0; csrid<='h3AF; csrid++)
|
||||
CSRArrayOld[csrid] = CSRArray[csrid];
|
||||
|
||||
// PMP ADDR 3B0 to 3EF
|
||||
for(csrid='h3B0; csrid<='h3EF; csrid++)
|
||||
CSRArrayOld[csrid] = CSRArray[csrid];
|
||||
end
|
||||
|
||||
// PMP CFG 3A0 to 3AF
|
||||
genvar index;
|
||||
for(index='h3A0; index<='h3AF; index++) begin
|
||||
assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
|
||||
assign rvvi.csr_wb[0][0][index] = CSR_W[index];
|
||||
assign rvvi.csr[0][0][index] = CSRArray[index];
|
||||
end
|
||||
|
||||
// PMP ADDR 3B0 to 3EF
|
||||
for(index='h3B0; index<='h3EF; index++) begin
|
||||
assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
|
||||
assign rvvi.csr_wb[0][0][index] = CSR_W[index];
|
||||
assign rvvi.csr[0][0][index] = CSRArray[index];
|
||||
end
|
||||
|
||||
assign rf[0] = 0;
|
||||
for(index = 1; index < NUMREGS; index += 1)
|
||||
assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
|
||||
@ -427,303 +398,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
||||
assign rvvi.f_wb[0][0][index] = frf_wb[index];
|
||||
end
|
||||
|
||||
// record previous csr value.
|
||||
integer index4;
|
||||
always_ff @(posedge clk) begin
|
||||
int csrid;
|
||||
// PMP CFG 3A0 to 3AF
|
||||
for(csrid='h3A0; csrid<='h3AF; csrid++)
|
||||
CSRArrayOld[csrid] = CSRArray[csrid];
|
||||
|
||||
// PMP ADDR 3B0 to 3EF
|
||||
for(csrid='h3B0; csrid<='h3EF; csrid++)
|
||||
CSRArrayOld[csrid] = CSRArray[csrid];
|
||||
|
||||
// M-mode trap CSRs
|
||||
CSRArrayOld[12'h300] = CSRArray[12'h300];
|
||||
CSRArrayOld[12'h302] = CSRArray[12'h302];
|
||||
CSRArrayOld[12'h303] = CSRArray[12'h303];
|
||||
CSRArrayOld[12'h304] = CSRArray[12'h304];
|
||||
CSRArrayOld[12'h305] = CSRArray[12'h305];
|
||||
CSRArrayOld[12'h340] = CSRArray[12'h340];
|
||||
CSRArrayOld[12'h341] = CSRArray[12'h341];
|
||||
CSRArrayOld[12'h342] = CSRArray[12'h342];
|
||||
CSRArrayOld[12'h343] = CSRArray[12'h343];
|
||||
CSRArrayOld[12'h344] = CSRArray[12'h344];
|
||||
|
||||
// S-mode trap CSRs
|
||||
CSRArrayOld[12'h100] = CSRArray[12'h100];
|
||||
CSRArrayOld[12'h104] = CSRArray[12'h104];
|
||||
CSRArrayOld[12'h105] = CSRArray[12'h105];
|
||||
CSRArrayOld[12'h140] = CSRArray[12'h140];
|
||||
CSRArrayOld[12'h141] = CSRArray[12'h141];
|
||||
CSRArrayOld[12'h142] = CSRArray[12'h142];
|
||||
CSRArrayOld[12'h143] = CSRArray[12'h143];
|
||||
CSRArrayOld[12'h144] = CSRArray[12'h144];
|
||||
|
||||
// Virtual Memory CSRs
|
||||
CSRArrayOld[12'h180] = CSRArray[12'h180] ;
|
||||
|
||||
// Floating-Point CSRs
|
||||
CSRArrayOld[12'h001] = CSRArray[12'h001];
|
||||
CSRArrayOld[12'h002] = CSRArray[12'h002];
|
||||
CSRArrayOld[12'h003] = CSRArray[12'h003];
|
||||
|
||||
// Counters / Performance Monitoring CSRs
|
||||
CSRArrayOld[12'h306] = CSRArray[12'h306];
|
||||
CSRArrayOld[12'h106] = CSRArray[12'h106];
|
||||
CSRArrayOld[12'h320] = CSRArray[12'h320];
|
||||
// mhpmevent3-31 not connected (232-33F)
|
||||
CSRArrayOld[12'hB00] = CSRArray[12'hB00];
|
||||
CSRArrayOld[12'hB02] = CSRArray[12'hB02];
|
||||
// mhpmcounter3-31 not connected (B03-B1F)
|
||||
// cycle, time, instret not connected (C00-C02)
|
||||
// hpmcounter3-31 not connected (C03-C1F)
|
||||
|
||||
// Machine Information Registers and Configuration CSRs
|
||||
CSRArrayOld[12'h301] = CSRArray[12'h301];
|
||||
CSRArrayOld[12'h30A] = CSRArray[12'h30A];
|
||||
CSRArrayOld[12'h10A] = CSRArray[12'h10A];
|
||||
CSRArrayOld[12'h747] = CSRArray[12'h747];
|
||||
CSRArrayOld[12'hF11] = CSRArray[12'hF11];
|
||||
CSRArrayOld[12'hF12] = CSRArray[12'hF12];
|
||||
CSRArrayOld[12'hF13] = CSRArray[12'hF13];
|
||||
CSRArrayOld[12'hF14] = CSRArray[12'hF14];
|
||||
CSRArrayOld[12'hF15] = CSRArray[12'hF15];
|
||||
|
||||
// Sstc CSRs
|
||||
CSRArrayOld[12'h14D] = CSRArray[12'h14D];
|
||||
|
||||
// Zkr CSRs
|
||||
// seed not connected (015)
|
||||
|
||||
// extra CSRs for RV32
|
||||
if (P.XLEN == 32) begin
|
||||
CSRArrayOld[12'h310] = CSRArray[12'h310];
|
||||
CSRArrayOld[12'h31A] = CSRArray[12'h31A];
|
||||
CSRArrayOld[12'h757] = CSRArray[12'h757];
|
||||
CSRArrayOld[12'h15D] = CSRArray[12'h15D];
|
||||
end
|
||||
end
|
||||
|
||||
// check for csr value change.
|
||||
// M-mode trap CSRs
|
||||
assign CSR_W[12'h300] = (CSRArrayOld[12'h300] != CSRArray[12'h300]) ? 1 : 0;
|
||||
assign CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0;
|
||||
assign CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0;
|
||||
assign CSR_W[12'h304] = (CSRArrayOld[12'h304] != CSRArray[12'h304]) ? 1 : 0;
|
||||
assign CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0;
|
||||
assign CSR_W[12'h340] = (CSRArrayOld[12'h340] != CSRArray[12'h340]) ? 1 : 0;
|
||||
assign CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0;
|
||||
assign CSR_W[12'h342] = (CSRArrayOld[12'h342] != CSRArray[12'h342]) ? 1 : 0;
|
||||
assign CSR_W[12'h343] = (CSRArrayOld[12'h343] != CSRArray[12'h343]) ? 1 : 0;
|
||||
assign CSR_W[12'h344] = (CSRArrayOld[12'h344] != CSRArray[12'h344]) ? 1 : 0;
|
||||
|
||||
// S-mode trap CSRs
|
||||
assign CSR_W[12'h100] = (CSRArrayOld[12'h100] != CSRArray[12'h100]) ? 1 : 0;
|
||||
assign CSR_W[12'h104] = (CSRArrayOld[12'h104] != CSRArray[12'h104]) ? 1 : 0;
|
||||
assign CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0;
|
||||
assign CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0;
|
||||
assign CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0;
|
||||
assign CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0;
|
||||
assign CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
|
||||
assign CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0;
|
||||
|
||||
// Virtual Memory CSRs
|
||||
assign CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0;
|
||||
|
||||
// Floating-Point CSRs
|
||||
assign CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
|
||||
assign CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
|
||||
assign CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
|
||||
|
||||
// Counters / Performance Monitoring CSRs
|
||||
assign CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0;
|
||||
assign CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0;
|
||||
assign CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0;
|
||||
// mhpmevent3-31 not connected (232-33F)
|
||||
assign CSR_W[12'hB00] = (CSRArrayOld[12'hB00] != CSRArray[12'hB00]) ? 1 : 0;
|
||||
assign CSR_W[12'hB02] = (CSRArrayOld[12'hB02] != CSRArray[12'hB02]) ? 1 : 0;
|
||||
// mhpmcounter3-31 not connected (B03-B1F)
|
||||
// cycle, time, instret not connected (C00-C02)
|
||||
// hpmcounter3-31 not connected (C03-C1F)
|
||||
|
||||
// Machine Information Registers and Configuration CSRs
|
||||
assign CSR_W[12'h301] = (CSRArrayOld[12'h301] != CSRArray[12'h301]) ? 1 : 0;
|
||||
assign CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0;
|
||||
assign CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0;
|
||||
assign CSR_W[12'h747] = (CSRArrayOld[12'h747] != CSRArray[12'h747]) ? 1 : 0;
|
||||
assign CSR_W[12'hF11] = (CSRArrayOld[12'hF11] != CSRArray[12'hF11]) ? 1 : 0;
|
||||
assign CSR_W[12'hF12] = (CSRArrayOld[12'hF12] != CSRArray[12'hF12]) ? 1 : 0;
|
||||
assign CSR_W[12'hF13] = (CSRArrayOld[12'hF13] != CSRArray[12'hF13]) ? 1 : 0;
|
||||
assign CSR_W[12'hF14] = (CSRArrayOld[12'hF14] != CSRArray[12'hF14]) ? 1 : 0;
|
||||
assign CSR_W[12'hF15] = (CSRArrayOld[12'hF15] != CSRArray[12'hF15]) ? 1 : 0;
|
||||
|
||||
// Sstc CSRs
|
||||
assign CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0;
|
||||
|
||||
// Zkr CSRs
|
||||
// seed not connected (015)
|
||||
|
||||
// extra CSRs for RV32
|
||||
if (P.XLEN == 32) begin
|
||||
assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0;
|
||||
assign CSR_W[12'h31A] = (CSRArrayOld[12'h31A] != CSRArray[12'h31A]) ? 1 : 0;
|
||||
assign CSR_W[12'h757] = (CSRArrayOld[12'h757] != CSRArray[12'h757]) ? 1 : 0;
|
||||
assign CSR_W[12'h15D] = (CSRArrayOld[12'h15D] != CSRArray[12'h15D]) ? 1 : 0;
|
||||
end
|
||||
|
||||
|
||||
|
||||
// M-mode trap CSRs
|
||||
assign rvvi.csr_wb[0][0][12'h300] = CSR_W[12'h300];
|
||||
assign rvvi.csr_wb[0][0][12'h302] = CSR_W[12'h302];
|
||||
assign rvvi.csr_wb[0][0][12'h303] = CSR_W[12'h303];
|
||||
assign rvvi.csr_wb[0][0][12'h304] = CSR_W[12'h304];
|
||||
assign rvvi.csr_wb[0][0][12'h305] = CSR_W[12'h305];
|
||||
assign rvvi.csr_wb[0][0][12'h340] = CSR_W[12'h340];
|
||||
assign rvvi.csr_wb[0][0][12'h341] = CSR_W[12'h341];
|
||||
assign rvvi.csr_wb[0][0][12'h342] = CSR_W[12'h342];
|
||||
assign rvvi.csr_wb[0][0][12'h343] = CSR_W[12'h343];
|
||||
assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344];
|
||||
|
||||
// S-mode trap CSRs
|
||||
assign rvvi.csr_wb[0][0][12'h100] = CSR_W[12'h100];
|
||||
assign rvvi.csr_wb[0][0][12'h104] = CSR_W[12'h104];
|
||||
assign rvvi.csr_wb[0][0][12'h105] = CSR_W[12'h105];
|
||||
assign rvvi.csr_wb[0][0][12'h140] = CSR_W[12'h140];
|
||||
assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141];
|
||||
assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142];
|
||||
assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
|
||||
assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144];
|
||||
|
||||
// Virtual Memory CSRs
|
||||
assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180];
|
||||
|
||||
// Floating-Point CSRs
|
||||
assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
|
||||
assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
|
||||
assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];
|
||||
|
||||
// Counters / Performance Monitoring CSRs
|
||||
assign rvvi.csr_wb[0][0][12'h306] = CSR_W[12'h306];
|
||||
assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106];
|
||||
assign rvvi.csr_wb[0][0][12'h320] = CSR_W[12'h320];
|
||||
// mhpmevent3-31 not connected (232-33F)
|
||||
assign rvvi.csr_wb[0][0][12'hB00] = CSR_W[12'hB00];
|
||||
assign rvvi.csr_wb[0][0][12'hB02] = CSR_W[12'hB02];
|
||||
// mhpmcounter3-31 not connected (B03-B1F)
|
||||
// cycle, time, instret not connected (C00-C02)
|
||||
// hpmcounter3-31 not connected (C03-C1F)
|
||||
|
||||
// Machine Information Registers and Configuration CSRs
|
||||
assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301];
|
||||
assign rvvi.csr_wb[0][0][12'h30A] = CSR_W[12'h30A];
|
||||
assign rvvi.csr_wb[0][0][12'h10A] = CSR_W[12'h10A];
|
||||
assign rvvi.csr_wb[0][0][12'h747] = CSR_W[12'h747];
|
||||
assign rvvi.csr_wb[0][0][12'hF11] = CSR_W[12'hF11];
|
||||
assign rvvi.csr_wb[0][0][12'hF12] = CSR_W[12'hF12];
|
||||
assign rvvi.csr_wb[0][0][12'hF13] = CSR_W[12'hF13];
|
||||
assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14];
|
||||
assign rvvi.csr_wb[0][0][12'hF15] = CSR_W[12'hF15];
|
||||
|
||||
// Sstc CSRs
|
||||
assign rvvi.csr_wb[0][0][12'h14D] = CSR_W[12'h14D];
|
||||
|
||||
// Zkr CSRs
|
||||
// seed not connected (015)
|
||||
|
||||
// extra CSRs for RV32
|
||||
if (P.XLEN == 32) begin
|
||||
assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310];
|
||||
assign rvvi.csr_wb[0][0][12'h31A] = CSR_W[12'h31A];
|
||||
assign rvvi.csr_wb[0][0][12'h757] = CSR_W[12'h757];
|
||||
assign rvvi.csr_wb[0][0][12'h15D] = CSR_W[12'h15D];
|
||||
end
|
||||
|
||||
|
||||
|
||||
// M-mode trap CSRs
|
||||
assign rvvi.csr[0][0][12'h300] = CSRArray[12'h300];
|
||||
assign rvvi.csr[0][0][12'h302] = CSRArray[12'h302];
|
||||
assign rvvi.csr[0][0][12'h303] = CSRArray[12'h303];
|
||||
assign rvvi.csr[0][0][12'h304] = CSRArray[12'h304];
|
||||
assign rvvi.csr[0][0][12'h305] = CSRArray[12'h305];
|
||||
assign rvvi.csr[0][0][12'h340] = CSRArray[12'h340];
|
||||
assign rvvi.csr[0][0][12'h341] = CSRArray[12'h341];
|
||||
assign rvvi.csr[0][0][12'h342] = CSRArray[12'h342];
|
||||
assign rvvi.csr[0][0][12'h343] = CSRArray[12'h343];
|
||||
assign rvvi.csr[0][0][12'h344] = CSRArray[12'h344];
|
||||
|
||||
// S-mode trap CSRs
|
||||
assign rvvi.csr[0][0][12'h100] = CSRArray[12'h100];
|
||||
assign rvvi.csr[0][0][12'h104] = CSRArray[12'h104];
|
||||
assign rvvi.csr[0][0][12'h105] = CSRArray[12'h105];
|
||||
assign rvvi.csr[0][0][12'h140] = CSRArray[12'h140];
|
||||
assign rvvi.csr[0][0][12'h141] = CSRArray[12'h141];
|
||||
assign rvvi.csr[0][0][12'h142] = CSRArray[12'h142];
|
||||
assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143];
|
||||
assign rvvi.csr[0][0][12'h144] = CSRArray[12'h144];
|
||||
|
||||
// Virtual Memory CSRs
|
||||
assign rvvi.csr[0][0][12'h180] = CSRArray[12'h180];
|
||||
|
||||
// Floating-Point CSRs
|
||||
assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001];
|
||||
assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002];
|
||||
assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003];
|
||||
|
||||
// Counters / Performance Monitoring CSRs
|
||||
assign rvvi.csr[0][0][12'h306] = CSRArray[12'h306];
|
||||
assign rvvi.csr[0][0][12'h106] = CSRArray[12'h106];
|
||||
assign rvvi.csr[0][0][12'h320] = CSRArray[12'h320];
|
||||
// mhpmevent3-31 not connected (232-33F)
|
||||
assign rvvi.csr[0][0][12'hB00] = CSRArray[12'hB00];
|
||||
assign rvvi.csr[0][0][12'hB02] = CSRArray[12'hB02];
|
||||
// mhpmcounter3-31 not connected (B03-B1F)
|
||||
// cycle, time, instret not connected (C00-C02)
|
||||
// hpmcounter3-31 not connected (C03-C1F)
|
||||
|
||||
// Machine Information Registers and Configuration CSRs
|
||||
assign rvvi.csr[0][0][12'h301] = CSRArray[12'h301];
|
||||
assign rvvi.csr[0][0][12'h30A] = CSRArray[12'h30A];
|
||||
assign rvvi.csr[0][0][12'h10A] = CSRArray[12'h10A];
|
||||
assign rvvi.csr[0][0][12'h747] = CSRArray[12'h747];
|
||||
assign rvvi.csr[0][0][12'hF11] = CSRArray[12'hF11];
|
||||
assign rvvi.csr[0][0][12'hF12] = CSRArray[12'hF12];
|
||||
assign rvvi.csr[0][0][12'hF13] = CSRArray[12'hF13];
|
||||
assign rvvi.csr[0][0][12'hF14] = CSRArray[12'hF14];
|
||||
assign rvvi.csr[0][0][12'hF15] = CSRArray[12'hF15];
|
||||
|
||||
// Sstc CSRs
|
||||
assign rvvi.csr[0][0][12'h14D] = CSRArray[12'h14D];
|
||||
|
||||
// Zkr CSRs
|
||||
// seed not connected (015)
|
||||
|
||||
// extra CSRs for RV32
|
||||
if (P.XLEN == 32) begin
|
||||
assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310];
|
||||
assign rvvi.csr[0][0][12'h31A] = CSRArray[12'h31A];
|
||||
assign rvvi.csr[0][0][12'h757] = CSRArray[12'h757];
|
||||
assign rvvi.csr[0][0][12'h15D] = CSRArray[12'h15D];
|
||||
end
|
||||
|
||||
|
||||
// PMP CFG 3A0 to 3AF
|
||||
for(index='h3A0; index<='h3AF; index++) begin
|
||||
assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
|
||||
assign rvvi.csr_wb[0][0][index] = CSR_W[index];
|
||||
assign rvvi.csr[0][0][index] = CSRArray[index];
|
||||
end
|
||||
|
||||
// PMP ADDR 3B0 to 3EF
|
||||
for(index='h3B0; index<='h3EF; index++) begin
|
||||
assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
|
||||
assign rvvi.csr_wb[0][0][index] = CSR_W[index];
|
||||
assign rvvi.csr[0][0][index] = CSRArray[index];
|
||||
end
|
||||
|
||||
// *** implementation only cancel? so sc does not clear?
|
||||
assign rvvi.lrsc_cancel[0][0] = 0;
|
||||
|
||||
@ -787,4 +461,3 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
||||
if(HaltW) $finish;
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user