diff --git a/README.md b/README.md index 32e363569..d8c2432d4 100644 --- a/README.md +++ b/README.md @@ -110,12 +110,12 @@ Ubuntu users may need to install and update various tools. Beware when cutting ### Install RISC-V GCC Cross-Compiler -To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V. This book is tested with GCC 12.2 (tagged 2022.09.21), but will likely work with newer versions as well. +To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V. This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. $ git clone https://github.com/riscv/riscv-gnu-toolchain $ cd riscv-gnu-toolchain - $ git checkout 2022.09.21 - $ ./configure --prefix=$RISCV --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + $ git checkout 2023.01.31 + $ ./configure --prefix=$RISCV --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" $ make --jobs Note: make --jobs will reduce compile time by compiling in parallel. However, adding this option could dramatically increase the memory utilization of your local machine. @@ -143,7 +143,7 @@ Spike also takes a while to install and compile, but this can be done concurrent $ git clone https://github.com/riscv-software-src/riscv-isa-sim $ mkdir riscv-isa-sim/build $ cd riscv-isa-sim/build - $ ../configure --prefix=$RISCV --enable-commitlog + $ ../configure --prefix=$RISCV $ make --jobs $ make install $ cd ../arch_test_target/spike/device diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 2b45d8e77..331ca13d6 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -54,13 +54,15 @@ fi cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain -./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" +git checkout 2023.01.31 +./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j ${NUM_THREADS} make install # elf2hex cd $RISCV -export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH +#export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH +gexport PATH=$RISCV/bin:$PATH git clone https://github.com/sifive/elf2hex.git cd elf2hex autoreconf -i @@ -87,7 +89,7 @@ cd $RISCV git clone https://github.com/riscv-software-src/riscv-isa-sim mkdir -p riscv-isa-sim/build cd riscv-isa-sim/build -../configure --prefix=$RISCV --enable-commitlog +../configure --prefix=$RISCV make -j ${NUM_THREADS} make install cd ../arch_test_target/spike/device diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index c5d5e7a1f..1fa1fe8e7 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -145,7 +145,7 @@ module csrsr ( STATUS_MXR_INT <= #1 0; STATUS_SUM_INT <= #1 0; STATUS_MPRV_INT <= #1 0; // Per Priv 3.3 - STATUS_FS_INT <= #1 `F_SUPPORTED ? 2'b01 : 2'b00; + STATUS_FS_INT <= #1 `F_SUPPORTED ? 2'b00 : 2'b00; // leave floating-point off until activated, even if F_SUPPORTED STATUS_MPP <= #1 0; STATUS_SPP <= #1 0; STATUS_MPIE <= #1 0; @@ -156,8 +156,6 @@ module csrsr ( STATUS_SBE <= #1 0; STATUS_UBE <= #1 0; end else if (~StallW) begin - if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #1 2'b11; // mark Float State dirty *** this should happen in M stage, be part of if/else; - if (TrapM) begin // Update interrupt enables per Privileged Spec p. 21 // y = PrivilegeModeW @@ -211,6 +209,6 @@ module csrsr ( STATUS_SPIE <= #1 `S_SUPPORTED & CSRWriteValM[5]; STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1]; STATUS_UBE <= #1 CSRWriteValM[6] & `U_SUPPORTED & `BIGENDIAN_SUPPORTED; - end + end else if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #1 2'b11; end endmodule diff --git a/tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py b/studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py similarity index 100% rename from tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py rename to studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py diff --git a/tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py b/studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py similarity index 100% rename from tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py rename to studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py diff --git a/tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py b/studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py similarity index 100% rename from tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py rename to studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py diff --git a/tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py b/studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py similarity index 100% rename from tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py rename to studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py diff --git a/tests/testgen/imperas/testgen-BRANCH.py b/studies/testgen/testgen-BRANCH.py similarity index 100% rename from tests/testgen/imperas/testgen-BRANCH.py rename to studies/testgen/testgen-BRANCH.py diff --git a/tests/testgen/imperas/testgen-CSR.py b/studies/testgen/testgen-CSR.py similarity index 100% rename from tests/testgen/imperas/testgen-CSR.py rename to studies/testgen/testgen-CSR.py diff --git a/tests/testgen/imperas/testgen-JAL-JALR.py b/studies/testgen/testgen-JAL-JALR.py similarity index 100% rename from tests/testgen/imperas/testgen-JAL-JALR.py rename to studies/testgen/testgen-JAL-JALR.py diff --git a/tests/testgen/imperas/testgen-LOAD.py b/studies/testgen/testgen-LOAD.py similarity index 100% rename from tests/testgen/imperas/testgen-LOAD.py rename to studies/testgen/testgen-LOAD.py diff --git a/tests/testgen/imperas/testgen-PIPELINE.py b/studies/testgen/testgen-PIPELINE.py similarity index 100% rename from tests/testgen/imperas/testgen-PIPELINE.py rename to studies/testgen/testgen-PIPELINE.py diff --git a/tests/testgen/imperas/testgen-SLL-SRL-SRA.py b/studies/testgen/testgen-SLL-SRL-SRA.py similarity index 100% rename from tests/testgen/imperas/testgen-SLL-SRL-SRA.py rename to studies/testgen/testgen-SLL-SRL-SRA.py diff --git a/tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py b/studies/testgen/testgen-SLLI-SRLI-SRAI.py similarity index 100% rename from tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py rename to studies/testgen/testgen-SLLI-SRLI-SRAI.py diff --git a/tests/testgen/imperas/testgen-SLTIU.py b/studies/testgen/testgen-SLTIU.py similarity index 100% rename from tests/testgen/imperas/testgen-SLTIU.py rename to studies/testgen/testgen-SLTIU.py diff --git a/tests/testgen/imperas/testgen-STORE.py b/studies/testgen/testgen-STORE.py similarity index 100% rename from tests/testgen/imperas/testgen-STORE.py rename to studies/testgen/testgen-STORE.py diff --git a/tests/testgen/imperas/testgen-VIRTUALMEMORY.py b/studies/testgen/testgen-VIRTUALMEMORY.py similarity index 100% rename from tests/testgen/imperas/testgen-VIRTUALMEMORY.py rename to studies/testgen/testgen-VIRTUALMEMORY.py diff --git a/tests/custom/debug/Makefile b/tests/custom/debug/Makefile index 9ee0b2e7b..ddabe4e31 100644 --- a/tests/custom/debug/Makefile +++ b/tests/custom/debug/Makefile @@ -2,8 +2,15 @@ TARGET = debug +$(TARGET).signature.output: $(TARGET).elf.memfile $(TARGET).elf + spike --isa=rv64gc +signature=$(TARGET).signature.output +signature-granularity=4 $(TARGET).elf +# diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit +# echo "Signature matches! Success!" + mkdir -p ../work + cp -f * ../work + $(TARGET).elf.memfile:$(TARGET).elf $(TARGET).elf.objdump.addr - riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $< --output $@ + riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@ $(TARGET).elf.objdump.addr: $(TARGET).elf.objdump extractFunctionRadix.sh $< @@ -15,13 +22,9 @@ $(TARGET).elf: $(TARGET).S Makefile riscv64-unknown-elf-gcc -g -o $(TARGET).elf -march=rv64gc -mabi=lp64 -mcmodel=medany \ -nostartfiles -T$(WALLY)/examples/link/link.ld $(TARGET).S -sim: - spike --isa=rv64gc +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET).elf - diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit - echo "Signature matches! Success!" clean: - rm -f $(TARGET).elf $(TARGET).elf.* + rm -f $(TARGET).elf $(TARGET).elf.* *.signature.output diff --git a/tests/custom/debug/debug.S b/tests/custom/debug/debug.S index 431a261e5..5be3c2012 100644 --- a/tests/custom/debug/debug.S +++ b/tests/custom/debug/debug.S @@ -5,6 +5,8 @@ .global rvtest_entry_point rvtest_entry_point: + lui t0, 0x1e # turn on Floating point and XS + csrs mstatus, t0 # openhwgroup/cvw Issue #55 la a6, begin_signature diff --git a/tests/testgen/testgen_header.S b/tests/testgen/testgen_header.S index 4129782f6..a93e5af10 100644 --- a/tests/testgen/testgen_header.S +++ b/tests/testgen/testgen_header.S @@ -1,21 +1,12 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 /////////////////////////////////////////// #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point @@ -23,4 +14,7 @@ rvtest_entry_point: RVMODEL_BOOT RVTEST_CODE_BEGIN +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",temp) + + RVTEST_SIGBASE( x6, wally_signature)