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marked possible improvement to ahb bus fsms.

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This commit is contained in:
Ross Thompson 2022-08-31 23:57:08 -05:00
parent 7598fbcb3b
commit eae56a890c
5 changed files with 7 additions and 5 deletions
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4
pipelined/src/ebu/abhinterface.sv
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@ -53,11 +53,11 @@ module ahbinterface #(parameter WRITEABLE = 0)
input logic CPUBusy, input logic CPUBusy,
output logic BusStall, output logic BusStall,
output logic BusCommitted, output logic BusCommitted,
output logic [`XLEN-1:0] ReadDataWordM); output logic [`XLEN-1:0] ReadDataWord);
logic CaptureEn; logic CaptureEn;
flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA), .q(ReadDataWordM)); flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA), .q(ReadDataWord));
if(WRITEABLE) begin if(WRITEABLE) begin
// delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN

1
pipelined/src/ebu/buscachefsm.sv
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@ -124,6 +124,7 @@ module buscachefsm #(parameter integer WordCountThreshold,
assign CacheAccess = BusCurrState == STATE_CACHE_FETCH | BusCurrState == STATE_CACHE_EVICT; assign CacheAccess = BusCurrState == STATE_CACHE_FETCH | BusCurrState == STATE_CACHE_EVICT;
assign BusStall = (BusCurrState == STATE_READY & (|RW | |CacheRW)) | assign BusStall = (BusCurrState == STATE_READY & (|RW | |CacheRW)) |
//(BusCurrState == STATE_CAPTURE & ~RW[0]) | // replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem.
(BusCurrState == STATE_CAPTURE) | (BusCurrState == STATE_CAPTURE) |
(BusCurrState == STATE_CACHE_FETCH) | (BusCurrState == STATE_CACHE_FETCH) |
(BusCurrState == STATE_CACHE_EVICT); (BusCurrState == STATE_CACHE_EVICT);

1
pipelined/src/ebu/busfsm.sv
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@ -71,6 +71,7 @@ module busfsm
end end
assign BusStall = (BusCurrState == STATE_READY & |RW) | assign BusStall = (BusCurrState == STATE_READY & |RW) |
// (BusCurrState == STATE_CAPTURE & ~RW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid.
(BusCurrState == STATE_CAPTURE); (BusCurrState == STATE_CAPTURE);
assign BusCommitted = BusCurrState != STATE_READY; assign BusCommitted = BusCurrState != STATE_READY;

2
pipelined/src/ifu/ifu.sv
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@ -252,7 +252,7 @@ module ifu (
ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY),
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
.HWSTRB(), .RW, .ByteMask(), .WriteData('0), .HWSTRB(), .RW, .ByteMask(), .WriteData('0),
.CPUBusy, .BusStall, .BusCommitted(), .ReadDataWordM(AllInstrRawF[31:0])); .CPUBusy, .BusStall, .BusCommitted(), .ReadDataWord(AllInstrRawF[31:0]));
assign IFUHBURST = 3'b0; assign IFUHBURST = 3'b0;
assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0; assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0;

2
pipelined/src/lsu/lsu.sv
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@ -294,7 +294,7 @@ module lsu (
ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY), ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY),
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
.HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), .HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
.CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWordM); .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWord(ReadDataWordM));
assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping
assign LSUHBURST = 3'b0; assign LSUHBURST = 3'b0;