From eaab1bfad45cfe20d15e62802030b4dee7d738e1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 15:47:36 -0800 Subject: [PATCH] Use CVW configuration in top-level --- pipelined/src/wally/wallypipelinedcore.sv | 85 ++++++++++------------- pipelined/src/wally/wallypipelinedsoc.sv | 14 ++-- 2 files changed, 43 insertions(+), 56 deletions(-) diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 2b71851f5..fa244b4f4 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -26,7 +26,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" +import cvw::*; // global CORE-V-Wally parameters + /* verilator lint_on UNUSED */ module wallypipelinedcore ( @@ -35,12 +36,12 @@ module wallypipelinedcore ( input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, // Bus Interface - input logic [`AHBW-1:0] HRDATA, + input logic [AHBW-1:0] HRDATA, input logic HREADY, HRESP, output logic HCLK, HRESETn, - output logic [`PA_BITS-1:0] HADDR, - output logic [`AHBW-1:0] HWDATA, - output logic [`XLEN/8-1:0] HWSTRB, + output logic [PA_BITS-1:0] HADDR, + output logic [AHBW-1:0] HWDATA, + output logic [XLEN/8-1:0] HWSTRB, output logic HWRITE, output logic [2:0] HSIZE, output logic [2:0] HBURST, @@ -58,15 +59,15 @@ module wallypipelinedcore ( logic IntDivE, W64E; logic CSRReadM, CSRWriteM, PrivilegedM; logic [1:0] AtomicM; - logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; - logic [`XLEN-1:0] SrcAM; + logic [XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; + logic [XLEN-1:0] SrcAM; logic [2:0] Funct3E; logic [31:0] InstrD; logic [31:0] InstrM; - logic [`XLEN-1:0] PCF, PCE, PCLinkE; - logic [`XLEN-1:0] PCM; - logic [`XLEN-1:0] CSRReadValW, MDUResultW; - logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F; + logic [XLEN-1:0] PCF, PCE, PCLinkE; + logic [XLEN-1:0] PCM; + logic [XLEN-1:0] CSRReadValW, MDUResultW; + logic [XLEN-1:0] UnalignedPCNextF, PCNext2F; logic [1:0] MemRWM; logic InstrValidM; logic InstrMisalignedFaultM; @@ -86,9 +87,9 @@ module wallypipelinedcore ( logic [4:0] RdE, RdM, RdW; logic FPUStallD; logic FWriteIntE; - logic [`FLEN-1:0] FWriteDataM; - logic [`XLEN-1:0] FIntResM; - logic [`XLEN-1:0] FCvtIntResW; + logic [FLEN-1:0] FWriteDataM; + logic [XLEN-1:0] FIntResM; + logic [XLEN-1:0] FCvtIntResW; logic FCvtIntW; logic FDivBusyE; logic IllegalFPUInstrM; @@ -96,23 +97,23 @@ module wallypipelinedcore ( logic FCvtIntStallD; logic FpLoadStoreM; logic [4:0] SetFflagsM; - logic [`XLEN-1:0] FIntDivResultW; + logic [XLEN-1:0] FIntDivResultW; // memory management unit signals logic ITLBWriteF; logic ITLBMissF; - logic [`XLEN-1:0] SATP_REGW; + logic [XLEN-1:0] SATP_REGW; logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; logic [1:0] STATUS_MPP, STATUS_FS; logic [1:0] PrivilegeModeW; - logic [`XLEN-1:0] PTE; + logic [XLEN-1:0] PTE; logic [1:0] PageType; logic sfencevmaM, WFIStallM; logic SelHPTW; // PMA checker signals - var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]; - var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; + var logic [XLEN-1:0] PMPADDR_ARRAY_REGW[PMP_ENTRIES-1:0]; + var logic [7:0] PMPCFG_ARRAY_REGW[PMP_ENTRIES-1:0]; // IMem stalls logic IFUStallF; @@ -120,14 +121,14 @@ module wallypipelinedcore ( // cpu lsu interface logic [2:0] Funct3M; - logic [`XLEN-1:0] IEUAdrE; - logic [`XLEN-1:0] WriteDataM; - logic [`XLEN-1:0] IEUAdrM; - logic [`LLEN-1:0] ReadDataW; + logic [XLEN-1:0] IEUAdrE; + logic [XLEN-1:0] WriteDataM; + logic [XLEN-1:0] IEUAdrM; + logic [LLEN-1:0] ReadDataW; logic CommittedM; // AHB ifu interface - logic [`PA_BITS-1:0] IFUHADDR; + logic [PA_BITS-1:0] IFUHADDR; logic [2:0] IFUHBURST; logic [1:0] IFUHTRANS; logic [2:0] IFUHSIZE; @@ -135,9 +136,9 @@ module wallypipelinedcore ( logic IFUHREADY; // AHB LSU interface - logic [`PA_BITS-1:0] LSUHADDR; - logic [`XLEN-1:0] LSUHWDATA; - logic [`XLEN/8-1:0] LSUHWSTRB; + logic [PA_BITS-1:0] LSUHADDR; + logic [XLEN-1:0] LSUHWDATA; + logic [XLEN/8-1:0] LSUHWSTRB; logic LSUHWRITE; logic LSUHREADY; @@ -161,11 +162,7 @@ module wallypipelinedcore ( logic BigEndianM; logic FCvtIntE; logic CommittedF; - - // Bit manipulation unit - logic [`XLEN-1:0] BMUResultE; // Bit manipuation result BMU -> IEU - logic BMUE; // is this a BMU instruction - + // instruction fetch unit: PC, branch prediction, instruction cache ifu ifu(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, @@ -193,7 +190,7 @@ module wallypipelinedcore ( .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, // Execute Stage interface .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, - .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE, + .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU @@ -203,7 +200,7 @@ module wallypipelinedcore ( .SrcAM, // to privilege and fpu .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, // Writeback stage - .CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), + .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[XLEN-1:0]), .InstrValidM, .FCvtIntResW, .FCvtIntW, // hazards .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, @@ -242,7 +239,7 @@ module wallypipelinedcore ( .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, .LSUStallM); - if(`BUS) begin : ebu + if(BUS) begin : ebu ebu ebu(// IFU connections .clk, .reset, // IFU interface @@ -280,7 +277,7 @@ module wallypipelinedcore ( .FlushD, .FlushE, .FlushM, .FlushW); // privileged unit - if (`ZICSR_SUPPORTED) begin:priv + if (ZICSR_SUPPORTED) begin:priv privileged priv( .clk, .reset, .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW, @@ -313,7 +310,7 @@ module wallypipelinedcore ( end // multiply/divide unit - if (`M_SUPPORTED) begin:mdu + if (M_SUPPORTED) begin:mdu mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .IntDivE, .W64E, @@ -324,12 +321,12 @@ module wallypipelinedcore ( end // floating point unit - if (`F_SUPPORTED) begin:fpu + if (F_SUPPORTED) begin:fpu fpu fpu( .clk, .reset, .FRM_REGW, // Rounding mode from CSR .InstrD, // instruction from IFU - .ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory + .ReadDataW(ReadDataW[FLEN-1:0]),// Read data from memory .ForwardedSrcAE, // Integer input being processed (from IEU) .StallE, .StallM, .StallW, // stall signals from HZU .FlushE, .FlushM, .FlushW, // flush signals from HZU @@ -360,15 +357,5 @@ module wallypipelinedcore ( assign SetFflagsM = 0; assign FpLoadStoreM = 0; end - - // bit manipulation unit - if (`B_SUPPORTED) begin:bmu - bmu bmu(.ForwardedSrcAE, .ForwardedSrcBE, .InstrD, .BMUE, .BMUResultE); - end else begin // no B instructions supported - assign BMUResultE = 0; - assign BMUE = 0; - end - - endmodule diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index 59f213ad0..26979545c 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -26,21 +26,21 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" +import cvw::*; // global CORE-V-Wally parameters module wallypipelinedsoc ( input logic clk, input logic reset_ext, // external asynchronous reset pin output logic reset, // reset synchronized to clk to prevent races on release // AHB Interface - input logic [`AHBW-1:0] HRDATAEXT, + input logic [AHBW-1:0] HRDATAEXT, input logic HREADYEXT, HRESPEXT, output logic HSELEXT, // outputs to external memory, shared with uncore memory output logic HCLK, HRESETn, - output logic [`PA_BITS-1:0] HADDR, - output logic [`AHBW-1:0] HWDATA, - output logic [`XLEN/8-1:0] HWSTRB, + output logic [PA_BITS-1:0] HADDR, + output logic [AHBW-1:0] HWDATA, + output logic [XLEN/8-1:0] HWSTRB, output logic HWRITE, output logic [2:0] HSIZE, output logic [2:0] HBURST, @@ -63,7 +63,7 @@ module wallypipelinedsoc ( ); // Uncore signals - logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore + logic [AHBW-1:0] HRDATA; // from AHB mux in uncore logic HRESP; // response from AHB logic MTimerInt, MSwInt; // timer and software interrupts from CLINT logic [63:0] MTIME_CLINT; // from CLINT to CSRs @@ -80,7 +80,7 @@ module wallypipelinedsoc ( ); // instantiate uncore if a bus interface exists - if (`BUS) begin : uncore + if (BUS) begin : uncore uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,