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cleanup of multimanager.

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This commit is contained in:
Ross Thompson 2022-08-31 11:38:06 -05:00
parent a0f681944c
commit eaa9cbda46
1 changed files with 18 additions and 18 deletions
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36
pipelined/src/ebu/ahbmultimanager.sv
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@ -72,7 +72,7 @@ module ahbmultimanager
localparam ADRBITS = $clog2(`XLEN/8); // address bits for Byte Mask generator localparam ADRBITS = $clog2(`XLEN/8); // address bits for Byte Mask generator
typedef enum logic [1:0] {IDLE, ARBITRATE} statetype; typedef enum logic [1:0] {IDLE, ARBITRATE} statetype;
statetype BusState, NextBusState; statetype CurrState, NextState;
logic LSUGrant; logic LSUGrant;
logic [ADRBITS-1:0] HADDRD; logic [ADRBITS-1:0] HADDRD;
logic [1:0] HSIZED; logic [1:0] HSIZED;
@ -106,7 +106,7 @@ module ahbmultimanager
// if two requests come in at once pick one to select and save the others Address phase // if two requests come in at once pick one to select and save the others Address phase
// inputs. // inputs. Abritration scheme is LSU always goes first.
// input stage IFU // input stage IFU
flopenr #(3+2+`PA_BITS) IFUSaveReg(HCLK, ~HRESETn, save[0], flopenr #(3+2+`PA_BITS) IFUSaveReg(HCLK, ~HRESETn, save[0],
@ -146,16 +146,16 @@ module ahbmultimanager
assign HWRITE = sel[1] ? LSUHWRITERestore : sel[0] ? 1'b0 : '0; assign HWRITE = sel[1] ? LSUHWRITERestore : sel[0] ? 1'b0 : '0;
// basic arb always selects LSU when both // basic arb always selects LSU when both
assign save[0] = BusState == IDLE & both; assign save[0] = CurrState == IDLE & both;
assign restore[0] = BusState == ARBITRATE; assign restore[0] = CurrState == ARBITRATE;
assign dis[0] = BusState == ARBITRATE; assign dis[0] = CurrState == ARBITRATE;
assign sel[0] = (NextBusState == ARBITRATE) ? 1'b0 : IFUReq; assign sel[0] = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
// //
assign save[1] = 1'b0; assign save[1] = 1'b0;
assign restore[1] = 1'b0; assign restore[1] = 1'b0;
assign dis[1] = 1'b0; assign dis[1] = 1'b0;
assign sel[1] = NextBusState == ARBITRATE ? 1'b1: LSUReq; assign sel[1] = NextState == ARBITRATE ? 1'b1: LSUReq;
@ -164,17 +164,17 @@ module ahbmultimanager
// while an cache line read is occuring, the line read finishes before // while an cache line read is occuring, the line read finishes before
// the data access can take place. // the data access can take place.
flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
always_comb always_comb
case (BusState) case (CurrState)
IDLE: if (both) NextBusState = ARBITRATE; IDLE: if (both) NextState = ARBITRATE;
else NextBusState = IDLE; else NextState = IDLE;
ARBITRATE: if (HREADY & WordCountFlag) NextBusState = IDLE; ARBITRATE: if (HREADY & WordCountFlag) NextState = IDLE;
else NextBusState = ARBITRATE; else NextState = ARBITRATE;
default: NextBusState = IDLE; default: NextState = IDLE;
endcase // case (BusState) endcase // case (CurrState)
assign DoArbitration = BusState == ARBITRATE; assign DoArbitration = CurrState == ARBITRATE;
assign HWDATA = LSUHWDATA; assign HWDATA = LSUHWDATA;
assign HWSTRB = LSUHWSTRB; assign HWSTRB = LSUHWSTRB;
@ -195,9 +195,9 @@ module ahbmultimanager
.q(WordCountDelayed)); .q(WordCountDelayed));
assign NextWordCount = WordCount + 1'b1; assign NextWordCount = WordCount + 1'b1;
assign CntReset = NextBusState == IDLE; assign CntReset = NextState == IDLE;
assign WordCountFlag = (WordCountDelayed == Threshold); // Detect when we are waiting on the final access. assign WordCountFlag = (WordCountDelayed == Threshold); // Detect when we are waiting on the final access.
assign WordCntEn = (NextBusState == ARBITRATE & HREADY); assign WordCntEn = (NextState == ARBITRATE & HREADY);
logic [2:0] HBURSTD; logic [2:0] HBURSTD;