From ea84211ff9b846ed93392c46ca629cdeb1fe9dbc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 4 Feb 2022 22:52:51 -0600 Subject: [PATCH] Removed unused ports from caches and buses. --- pipelined/src/cache/cache.sv | 17 +---------------- pipelined/src/ifu/ifu.sv | 4 ++-- pipelined/src/lsu/busdp.sv | 16 ++++++---------- pipelined/src/lsu/lsu.sv | 8 ++------ 4 files changed, 11 insertions(+), 34 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index e08b65e87..b2e6d2391 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -56,8 +56,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( input logic CacheBusAck, output logic [`PA_BITS-1:0] CacheBusAdr, input logic [LINELEN-1:0] CacheMemWriteData, - output logic [LINELEN-1:0] ReadDataLine, - output logic [`XLEN-1:0] ReadDataLineSets [(LINELEN/`XLEN)-1:0]); + output logic [LINELEN-1:0] ReadDataLine); // Cache parameters localparam LINEBYTELEN = LINELEN/8; @@ -151,20 +150,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, WayHitRaw, WayHitSaved); mux2 #(NUMWAYS) saverestoremux(WayHitRaw, WayHitSaved, restore, WayHit); - - // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can - // easily build a variable input mux. - // *** move this to LSU and IFU, also remove mux from busdp into LSU. - // *** give this a module name to match block diagram - genvar index; - if(DCACHE == 1) begin: readdata - // *** only here temporary - for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux - assign ReadDataLineSets[index] = ReadDataLine[((index+1)*`XLEN)-1: (index*`XLEN)]; - end - end else begin: readdata - end - ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write Enables ///////////////////////////////////////////////////////////////////////////////////////////// diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 31038bff5..2505b6575 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -194,7 +194,7 @@ module ifu ( .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), .WordCount(), .LSUBusHWDATA(), - .ReadDataLineSetsM(), .DCacheFetchLine(ICacheFetchLine), + .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck), .DCacheMemWriteData(ICacheMemWriteData), .LSUPAdrM(PCPF), .FinalAMOWriteDataM(), .ReadDataWordM(FinalInstrRawF), .ReadDataWordMuxM(AllInstrRawF[31:0]), @@ -216,7 +216,7 @@ module ifu ( .CacheMemWriteData(ICacheMemWriteData), .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheFetchLine(ICacheFetchLine), - .CacheWriteLine(), .ReadDataLineSets(), .ReadDataLine(ReadDataLine), + .CacheWriteLine(), .ReadDataLine(ReadDataLine), .save, .restore, .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), .FinalWriteData('0), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index fc43d0c1a..f4b2bb234 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -49,7 +49,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0) output logic [LOGWPL-1:0] WordCount, // cache interface. input logic [`PA_BITS-1:0] DCacheBusAdr, - input var logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0], input logic DCacheFetchLine, input logic DCacheWriteLine, output logic DCacheBusAck, @@ -83,18 +82,15 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0) mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr); assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr; - //assign PreLSUBusHWDATA = ReadDataWordM;// ReadDataLineSetsM[WordCount]; // only in lsu, not ifu - // this mux is only used in the LSU's bus. if(LSU == 1) mux2 #(`XLEN) lsubushwdatamux( .d0(ReadDataWordM), .d1(FinalAMOWriteDataM), - .s(SelUncachedAdr), .y(LSUBusHWDATA)); + .s(SelUncachedAdr), .y(LSUBusHWDATA)); else assign LSUBusHWDATA = '0; - - mux2 #(3) lsubussizemux( - .d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(LSUBusSize)); - mux2 #(WORDLEN) UnCachedDataMux( - .d0(ReadDataWordM), .d1(DCacheMemWriteData[WORDLEN-1:0]), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); + mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), + .s(SelUncachedAdr), .y(LSUBusSize)); + mux2 #(WORDLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheMemWriteData[WORDLEN-1:0]), + .s(SelUncachedAdr), .y(ReadDataWordMuxM)); - busfsm #(WordCountThreshold, LOGWPL, (`DMEM == `MEM_CACHE)) // *** cleanup + busfsm #(WordCountThreshold, LOGWPL, (`DMEM == `MEM_CACHE)) // *** cleanup Icache? must fix. busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, .LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusRead, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 80e5ebfd8..c078ec897 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -175,7 +175,6 @@ module lsu ( logic [`XLEN-1:0] ReadDataWordMuxM; logic SelUncachedAdr; - if (`DMEM == `MEM_TIM) begin : dtim dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, @@ -196,19 +195,16 @@ module lsu ( logic [`PA_BITS-1:0] WordOffsetAddr; logic SelBus; logic [LOGWPL-1:0] WordCount; - logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0]; - logic [`PA_BITS-1-`XLEN/8-LOGWPL:0] Pad; busdp #(WORDSPERLINE, LINELEN, `XLEN, LOGWPL, 1) busdp( .clk, .reset, .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .WordCount, - .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .ReadDataLineSetsM, .DCacheFetchLine, + .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, .DCacheMemWriteData, .LSUPAdrM, .FinalAMOWriteDataM, .ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); - assign Pad = '0; assign WordOffsetAddr = LSUBusWrite ? ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) : LSUPAdrM; subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( @@ -225,7 +221,7 @@ module lsu ( .FinalWriteData(FinalWriteDataM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequest, .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), - .ReadDataLineSets(ReadDataLineSetsM), .ReadDataLine(ReadDataLineM), .CacheMemWriteData(DCacheMemWriteData), + .ReadDataLine(ReadDataLineM), .CacheMemWriteData(DCacheMemWriteData), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));