From 6e1d4ec4edeccec2d211dee45da04bdce3a5af2d Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 16 Jul 2022 17:43:31 -0700 Subject: [PATCH 1/4] restored intPending logic to be sticky for PLIC --- pipelined/src/uncore/plic_apb.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/uncore/plic_apb.sv b/pipelined/src/uncore/plic_apb.sv index f83033c4d..51e94d7f4 100644 --- a/pipelined/src/uncore/plic_apb.sv +++ b/pipelined/src/uncore/plic_apb.sv @@ -172,8 +172,8 @@ module plic_apb ( end // pending interrupt requests - //assign nextIntPending = (intPending | requests) & ~intInProgress; // - assign nextIntPending = requests; // DH: RT made this change May 2022, but it seems to be a bug to not consider intInProgress; see May 23, 2022 slack discussion + assign nextIntPending = (intPending | requests) & ~intInProgress; // dh changed back 7/9/22 see if Buildroot still boots. Confirmed to boot successfully. + //assign nextIntPending = requests; // DH: RT made this change May 2022, but it seems to be a bug to not consider intInProgress; see May 23, 2022 slack discussion flopr #(`N) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending); // context-dependent signals From 2a965cf634685bee8115063a08612a27de60b9e0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 17 Jul 2022 01:39:57 +0000 Subject: [PATCH 2/4] Don't delete hdl directory at end of run --- synthDC/Makefile | 2 +- synthDC/extractSummary.py | 7 +++++++ synthDC/scripts/synth.tcl | 2 +- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 369529e39..98b719428 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -107,7 +107,7 @@ ifeq ($(SAIFPOWER), 1) cp -f ../pipelined/regression/power.saif . endif dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out - rm -rf $(OUTPUTDIR)/hdl +# rm -rf $(OUTPUTDIR)/hdl rm -rf $(OUTPUTDIR)/WORK rm -rf $(OUTPUTDIR)/alib-52 diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 93363a069..29e1c8024 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -78,6 +78,13 @@ def freqPlot(tech, width, config): ''' plots delay, area for syntheses with specified tech, module, width ''' + current_directory = os.getcwd() + final_directory = os.path.join(current_directory, 'plots/wally') +# if not os.path.exists(final_directory): +# os.makedirs(final_directory) +# os.chdir(final_directory) + + freqsL, delaysL, areasL = ([[], []] for i in range(3)) for oneSynth in allSynths: if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special): diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 251522dc8..9b72849f8 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -56,7 +56,7 @@ set vhdlout_show_unconnected_pins "true" # Due to parameterized Verilog must use analyze/elaborate and not # read_verilog/vhdl (change to pull in Verilog and/or VHDL) # -set alib_library_analysis_path ./$outputDir +#set alib_library_analysis_path ./$outputDir define_design_lib WORK -path ./$outputDir/WORK analyze -f sverilog -lib WORK $my_verilog_files elaborate $my_toplevel -lib WORK From 3815f197633a140c4237566e460cf8690ec86f88 Mon Sep 17 00:00:00 2001 From: James Stine Date: Sun, 17 Jul 2022 11:06:30 -0500 Subject: [PATCH 3/4] Add import os in extractSummary.py --- synthDC/extractSummary.py | 1 + 1 file changed, 1 insertion(+) diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 29e1c8024..d4f86fb3e 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -11,6 +11,7 @@ import numpy as np from ppa.ppaAnalyze import noOutliers from matplotlib import ticker import argparse +import os def synthsintocsv(): From 2753699fb2737d39027f7801f5686b9722f1a7f2 Mon Sep 17 00:00:00 2001 From: James Stine Date: Sun, 17 Jul 2022 13:00:44 -0500 Subject: [PATCH 4/4] Add back extractSummary mkdir plots --- synthDC/extractSummary.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index d4f86fb3e..978365b16 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -60,6 +60,7 @@ def synthsintocsv(): writer.writerow([width, config, special, tech, freq, delay, area]) file.close() + def synthsfromcsv(filename): Synth = namedtuple("Synth", "width config special tech freq delay area") with open(filename, newline='') as csvfile: @@ -75,16 +76,15 @@ def synthsfromcsv(filename): allSynths[i] = Synth(*allSynths[i]) return allSynths + def freqPlot(tech, width, config): ''' plots delay, area for syntheses with specified tech, module, width ''' current_directory = os.getcwd() final_directory = os.path.join(current_directory, 'plots/wally') -# if not os.path.exists(final_directory): -# os.makedirs(final_directory) -# os.chdir(final_directory) - + if not os.path.exists(final_directory): + os.makedirs(final_directory) freqsL, delaysL, areasL = ([[], []] for i in range(3)) for oneSynth in allSynths: @@ -159,6 +159,7 @@ def areaDelay(tech, delays, areas, labels, fig, ax, norm=False): return fig + def plotFeatures(tech, width, config): delays, areas, labels = ([] for i in range(3)) freq = techdict[tech].targfreq @@ -176,7 +177,8 @@ def plotFeatures(tech, width, config): titlestr = tech+'_'+width+config plt.title(titlestr) plt.savefig('./plots/wally/features_'+titlestr+'.png') - + + def plotConfigs(tech, special=''): delays, areas, labels = ([] for i in range(3)) freq = techdict[tech].targfreq @@ -215,7 +217,8 @@ def normAreaDelay(special=''): ax.set_ylabel('Area (add32)') ax.legend(handles = fullLeg, loc='upper left') plt.savefig('./plots/wally/normAreaDelay.png') - + + def addFO4axis(fig, ax, tech): fo4 = techdict[tech].fo4