diff --git a/src/ieu/aes_common/rconlut128.sv b/src/ieu/aes_common/rconlut128.sv new file mode 100644 index 000000000..3360b9b51 --- /dev/null +++ b/src/ieu/aes_common/rconlut128.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// rconlut128.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: rcon lookup for aes64ks1i instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module rconlut128( + input logic [3:0] rd, + output logic [7:0] rconOut +); + + always_comb + case(rd) + 4'h0 : rconOut = 8'h01; + 4'h1 : rconOut = 8'h02; + 4'h2 : rconOut = 8'h04; + 4'h3 : rconOut = 8'h08; + 4'h4 : rconOut = 8'h10; + 4'h5 : rconOut = 8'h20; + 4'h6 : rconOut = 8'h40; + 4'h7 : rconOut = 8'h80; + 4'h8 : rconOut = 8'h1b; + 4'h9 : rconOut = 8'h36; + 4'hA : rconOut = 8'h00; + default : rconOut = 8'h00; + endcase +endmodule diff --git a/src/ieu/aes_instructions/aes32dsi.sv b/src/ieu/aes_instructions/aes32dsi.sv index 5f0b20302..79d08e889 100644 --- a/src/ieu/aes_instructions/aes32dsi.sv +++ b/src/ieu/aes_instructions/aes32dsi.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes32dsi instruction +// Purpose: aes32dsi instruction: RV32 final round AES decryption // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/aes_instructions/aes32dsmi.sv b/src/ieu/aes_instructions/aes32dsmi.sv index 5eecc5e30..6ba703f26 100644 --- a/src/ieu/aes_instructions/aes32dsmi.sv +++ b/src/ieu/aes_instructions/aes32dsmi.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes32dsmi instruction +// Purpose: aes32dsmi instruction: RV32 middle round AES decryption // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/aes_instructions/aes32esi.sv b/src/ieu/aes_instructions/aes32esi.sv index fc502c10e..dd7b165dc 100644 --- a/src/ieu/aes_instructions/aes32esi.sv +++ b/src/ieu/aes_instructions/aes32esi.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes32esi instruction +// Purpose: aes32esi instruction: : RV32 final round AES encryption // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/aes_instructions/aes32esmi.sv b/src/ieu/aes_instructions/aes32esmi.sv index 42ca4cd33..30a48ca1b 100644 --- a/src/ieu/aes_instructions/aes32esmi.sv +++ b/src/ieu/aes_instructions/aes32esmi.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes32esmi instruction +// Purpose: aes32esmi instruction: RV32 middle round AES encryption // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/aes_instructions/aes64ds.sv b/src/ieu/aes_instructions/aes64ds.sv index f984df604..fb3ea0609 100644 --- a/src/ieu/aes_instructions/aes64ds.sv +++ b/src/ieu/aes_instructions/aes64ds.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes64ds instruction +// Purpose: aes64ds instruction: RV64 final round decryption // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/aes_instructions/aes64dsm.sv b/src/ieu/aes_instructions/aes64dsm.sv index 529ff8af0..995643f6d 100644 --- a/src/ieu/aes_instructions/aes64dsm.sv +++ b/src/ieu/aes_instructions/aes64dsm.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes64dsm instruction +// Purpose: aes64dsm instruction: RV64 middle round decryption // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/aes_instructions/aes64es.sv b/src/ieu/aes_instructions/aes64es.sv index c9d7c6bc2..62fc06822 100644 --- a/src/ieu/aes_instructions/aes64es.sv +++ b/src/ieu/aes_instructions/aes64es.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes64es instruction +// Purpose: aes64es instruction: RV64 final round encryption // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/aes_instructions/aes64esm.sv b/src/ieu/aes_instructions/aes64esm.sv index 34806bf85..1f51522de 100644 --- a/src/ieu/aes_instructions/aes64esm.sv +++ b/src/ieu/aes_instructions/aes64esm.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes64esm instruction +// Purpose: aes64esm instruction: RV64 middle round encryption // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/aes_instructions/aes64im.sv b/src/ieu/aes_instructions/aes64im.sv index 905805802..fe2a4f0fb 100644 --- a/src/ieu/aes_instructions/aes64im.sv +++ b/src/ieu/aes_instructions/aes64im.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes64im instruction +// Purpose: aes64im instruction: RV64 accelerator mixcolumns and create decryption keyschedule // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/aes_instructions/aes64ks1i.sv b/src/ieu/aes_instructions/aes64ks1i.sv index e2e8a2525..824555f00 100644 --- a/src/ieu/aes_instructions/aes64ks1i.sv +++ b/src/ieu/aes_instructions/aes64ks1i.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes64ks1i instruction +// Purpose: aes64ks1i instruction: part of AES keyschedule with involving sbox // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -39,7 +39,7 @@ module aes64ks1i( logic [31:0] SboxOut; // Get rcon value from table - rconlut128 rc(.RD(roundnum), .rconOut(rconPreShift)); + rconlut128 rc(.rd(roundnum), .rconOut(rconPreShift)); // Shift RCON value assign rcon = {24'b0, rconPreShift}; diff --git a/src/ieu/aes_instructions/aes64ks2.sv b/src/ieu/aes_instructions/aes64ks2.sv index 46833ab33..0d7a84b32 100644 --- a/src/ieu/aes_instructions/aes64ks2.sv +++ b/src/ieu/aes_instructions/aes64ks2.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes64ks2 instruction +// Purpose: aes64ks2 instruction: part of AES keyschedule // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/kmu/zbkb.sv b/src/ieu/kmu/zbkb.sv index ca6214edb..90b774042 100644 --- a/src/ieu/kmu/zbkb.sv +++ b/src/ieu/kmu/zbkb.sv @@ -4,7 +4,7 @@ // Written: kelvin.tran@okstate.edu, james.stine@okstate.edu // Created: 4 October 2023 // -// Purpose: RISC-V ZBKB top level unit +// Purpose: RISC-V ZBKB top level unit: bit manipulation instructions for crypto // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/kmu/zbkx.sv b/src/ieu/kmu/zbkx.sv index 9bf48406a..5797195ec 100644 --- a/src/ieu/kmu/zbkx.sv +++ b/src/ieu/kmu/zbkx.sv @@ -4,7 +4,7 @@ // Written: kelvin.tran@okstate.edu, james.stine@okstate.edu // Created: 1 February 2024 // -// Purpose: RISC-V ZBKX top level unit +// Purpose: RISC-V ZBKX top level unit: crossbar permutation instructions for crypto // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/kmu/zknd32.sv b/src/ieu/kmu/zknd32.sv index 4eb3ffedc..e6f1a5c16 100644 --- a/src/ieu/kmu/zknd32.sv +++ b/src/ieu/kmu/zknd32.sv @@ -5,7 +5,7 @@ // Created: 27 November 2023 // Modified: 31 January 2024 // -// Purpose: RISC-V ZKND top level unit for 32-bit instructions +// Purpose: RISC-V ZKND top level unit for 32-bit instructions: RV32 NIST AES Decryption // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/kmu/zknd64.sv b/src/ieu/kmu/zknd64.sv index b48e88476..78ad47cb9 100644 --- a/src/ieu/kmu/zknd64.sv +++ b/src/ieu/kmu/zknd64.sv @@ -5,7 +5,7 @@ // Created: 27 November 2023 // Modified: 31 January 2024 // -// Purpose: RISC-V ZKND top level unit for 64-bit instructions +// Purpose: RISC-V ZKND top level unit for 64-bit instructions: RV64 NIST AES Decryption // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/kmu/zkne32.sv b/src/ieu/kmu/zkne32.sv index 578345628..a595d975e 100644 --- a/src/ieu/kmu/zkne32.sv +++ b/src/ieu/kmu/zkne32.sv @@ -5,7 +5,7 @@ // Created: 21 November 2023 // Modified: 31 January 2024 // -// Purpose: RISC-V ZKNE top level unit for 32-bit instructions +// Purpose: RISC-V ZKNE top level unit for 32-bit instructions: RV32 NIST AES Encryption // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/kmu/zkne64.sv b/src/ieu/kmu/zkne64.sv index 6cfe94a78..fbba056a7 100644 --- a/src/ieu/kmu/zkne64.sv +++ b/src/ieu/kmu/zkne64.sv @@ -5,7 +5,7 @@ // Created: 21 November 2023 // Modified: 31 January 2024 // -// Purpose: RISC-V ZKNE top level unit for 64-bit instructions +// Purpose: RISC-V ZKNE top level unit for 64-bit instructions: RV64 NIST AES Encryption // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/kmu/zknh32.sv b/src/ieu/kmu/zknh32.sv index d9118f3f6..6d297f363 100644 --- a/src/ieu/kmu/zknh32.sv +++ b/src/ieu/kmu/zknh32.sv @@ -4,7 +4,7 @@ // Written: kelvin.tran@okstate.edu, james.stine@okstate.edu // Created: 13 February 2024 // -// Purpose: RISC-V ZKNH 32-Bit top level unit +// Purpose: RISC-V ZKNH 32-Bit top level unit: RV32 NIST Hash // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/kmu/zknh64.sv b/src/ieu/kmu/zknh64.sv index ed5886cef..198f03044 100644 --- a/src/ieu/kmu/zknh64.sv +++ b/src/ieu/kmu/zknh64.sv @@ -4,7 +4,7 @@ // Written: kelvin.tran@okstate.edu, james.stine@okstate.edu // Created: 13 February 2024 // -// Purpose: RISC-V ZKNH 64-Bit top level unit +// Purpose: RISC-V ZKNH 64-Bit top level unit: RV64 NIST Hash // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw