From 2aecf688f9acbcdce2de82490ec1dcbc2afb8f21 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 23 Oct 2023 15:29:50 -0500 Subject: [PATCH 1/5] Addeed script to sweep sim_bp for btb. --- bin/CModelBTBAccuracy.sh | 57 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100755 bin/CModelBTBAccuracy.sh diff --git a/bin/CModelBTBAccuracy.sh b/bin/CModelBTBAccuracy.sh new file mode 100755 index 000000000..5cde4238c --- /dev/null +++ b/bin/CModelBTBAccuracy.sh @@ -0,0 +1,57 @@ +#!/bin/bash + +########################################### +## Written: ross1728@gmail.com +## Created: 23 October 2023 +## Modified: +## +## Purpose: Takes a directory of branch outcomes organized as 1 files per benchmark. +## Computes the geometric mean for btb accuracy +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + + +Directory="$1" +Files="$1/*.log" + +for Size in $(seq 6 2 16) +do + Product=1.0 + Count=0 + BMDRArray=() + for File in $Files + do + lines=`sim_bp gshare 16 16 $Size 1 $File | tail -5` + Total=`echo "$lines" | head -1 | awk '{print $5}'` + Miss=`echo "$lines" | tail -2 | head -1 | awk '{print $8}'` + BMDR=`echo "$Miss / $Total" | bc -l` + BMDRArray+=("$BMDR") + if [ $Miss -eq 0 ]; then + Product=`echo "scale=200; $Product / $Total" | bc -l` + else + Product=`echo "scale=200; $Product * $Miss / $Total" | bc -l` + fi + Count=$((Count+1)) + done + # with such long precision bc outputs onto multiple lines + # must remove \n and \ from string + Product=`echo "$Product" | tr -d '\n' | tr -d '\\\'` + GeoMean=`perl -E "say $Product**(1/$Count)"` + echo "$Pred$Size $GeoMean" +done From 1611d5ec3c777ef230ed9513c4c902c57742f682 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 23 Oct 2023 15:30:43 -0500 Subject: [PATCH 2/5] Fixed issue 250. instruction classification was not correct for jalr ra (non zero). --- src/ifu/bpred/icpred.sv | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv index 65e60c59c..70136bdaf 100644 --- a/src/ifu/bpred/icpred.sv +++ b/src/ifu/bpred/icpred.sv @@ -51,20 +51,20 @@ module icpred import cvw::*; #(parameter cvw_t P, // An alternative to using the BTB to store the instruction class is to partially decode // the instructions in the Fetch stage into, Call, Return, Jump, and Branch instructions. // This logic is not described in the text book as of 23 February 2023. - logic ccall, cj, cjr, ccallr, CJumpF, CBranchF; + logic cjal, cj, cjr, cjalr, CJumpF, CBranchF; logic NCJumpF, NCBranchF; if(P.C_SUPPORTED) begin logic [4:0] CompressedOpcF; assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; - assign ccall = CompressedOpcF == 5'h09 & P.XLEN == 32; + assign cjal = CompressedOpcF == 5'h09 & P.XLEN == 32; assign cj = CompressedOpcF == 5'h0d; assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; - assign ccallr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; - assign CJumpF = ccall | cj | cjr | ccallr; + assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + assign CJumpF = cjal | cj | cjr | cjalr; assign CBranchF = CompressedOpcF[4:1] == 4'h7; end else begin - assign {ccall, cj, cjr, ccallr, CJumpF, CBranchF} = '0; + assign {cjal, cj, cjr, cjalr, CJumpF, CBranchF} = '0; end assign NCJumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F; @@ -72,11 +72,11 @@ module icpred import cvw::*; #(parameter cvw_t P, assign BPBranchF = NCBranchF | (P.C_SUPPORTED & CBranchF); assign BPJumpF = NCJumpF | (P.C_SUPPORTED & (CJumpF)); - assign BPReturnF = (NCJumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01) | // returnurn must returnurn to ra or r5 - (P.C_SUPPORTED & (ccallr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); + assign BPReturnF = (NCJumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 & PostSpillInstrRawF[11:7] == 5'b0) | // return must return to ra or r5 + (P.C_SUPPORTED & cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); assign BPCallF = (NCJumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // call(r) must link to ra or x5 - (P.C_SUPPORTED & (ccall | (ccallr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); + (P.C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); end else begin // This section connects the BTB's instruction class prediction. From 694ec189342a03291d8a638e289c3ecea45a32b0 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 23 Oct 2023 15:32:03 -0500 Subject: [PATCH 3/5] Added support for branch counters when there is no branch predictor. --- src/ifu/ifu.sv | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index af6f70898..5ecc0237c 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -340,8 +340,21 @@ module ifu import cvw::*; #(parameter cvw_t P) ( end else begin : bpred mux2 #(P.XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF)); + logic BranchM, JumpM, BranchW, JumpW; + logic CallD, CallE, CallM, CallW; + logic ReturnD, ReturnE, ReturnM, ReturnW; assign BPWrongE = PCSrcE; - assign {InstrClassM, BPDirPredWrongM, BTAWrongM, RASPredPCWrongM, IClassWrongM} = '0; + icpred #(P, 0) icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW, + .CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, + .BTBCallF(1'b0), .BTBReturnF(1'b0), .BTBJumpF(1'b0), + .BTBBranchF(1'b0), .BPCallF(), .BPReturnF(), .BPJumpF(), .BPBranchF(), .IClassWrongM, + .IClassWrongE(), .BPReturnWrongD()); + flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, BPWrongM); + assign RASPredPCWrongM = '0; + assign BPDirPredWrongM = BPWrongM; + assign BTAWrongM = BPWrongM; + assign InstrClassM = {CallM, ReturnM, JumpM, BranchM}; assign NextValidPCE = PCE; end From ea403e02ffd5daf288a5efd9157b11689bfb3f47 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 23 Oct 2023 16:09:40 -0500 Subject: [PATCH 4/5] Updated bpred-sim.py to take command line options to select between sweeping direction, target, class, or ras prediction. --- sim/bpred-sim.py | 117 ++++++++++++++++++++++++++--------------------- 1 file changed, 65 insertions(+), 52 deletions(-) diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py index 9a59e8866..9e7ec12a6 100755 --- a/sim/bpred-sim.py +++ b/sim/bpred-sim.py @@ -11,6 +11,7 @@ # ################################## import sys,os,shutil +import argparse class bcolors: HEADER = '\033[95m' @@ -46,55 +47,6 @@ configs = [ ) ] -# bpdSize = [6, 8, 10, 12, 14, 16] -# bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic'] -# for CurrBPType in bpdType: -# for CurrBPSize in bpdSize: -# name = CurrBPType+str(CurrBPSize) -# configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=" + str(bpdType.index(CurrBPType)) + "+define+BPRED_SIZE=" + str(CurrBPSize) -# tc = TestCase( -# name=name, -# variant="rv32gc", -# cmd="vsim > {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < Date: Tue, 24 Oct 2023 10:29:02 -0500 Subject: [PATCH 5/5] Fixed bug in bpred-sim.py for btb and class size sweep. --- sim/bpred-sim.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py index 9e7ec12a6..209e21fc4 100755 --- a/sim/bpred-sim.py +++ b/sim/bpred-sim.py @@ -119,7 +119,7 @@ def main(): bpdSize = [6, 8, 10, 12, 14, 16] for CurrBPSize in bpdSize: name = 'BTB'+str(CurrBPSize) - configOptions = "+define+INSTR_CLASS_PRED=1 +define+BPRED_OVERRIDE +define+BPRED_TYPE=\`BP_GSHARE" + "+define+BPRED_SIZE=16" + "+define+BTB_SIZE=" + str(CurrBPSize) + "+define+BTB_OVERRIDE" + configOptions = "+define+INSTR_CLASS_PRED=1 +define+BPRED_OVERRIDE +define+BPRED_TYPE=\`BP_GSHARE" + "+define+BPRED_SIZE=16" + "+define+RAS_SIZE=16+define+BTB_SIZE=" + str(CurrBPSize) + "+define+BTB_OVERRIDE" tc = TestCase( name=name, variant="rv32gc",