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	Fixed .gitignore
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							@ -8,6 +8,7 @@ __pycache__/
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#External repos
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					#External repos
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addins
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					addins
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					addins/riscv-arch-test/Makefile.include
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#vsim work files to ignore
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					#vsim work files to ignore
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transcript
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					transcript
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@ -43,3 +44,7 @@ fpga/generator/WallyFPGA*
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fpga/generator/reports/
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					fpga/generator/reports/
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fpga/generator/*.log
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					fpga/generator/*.log
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fpga/generator/*.jou
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					fpga/generator/*.jou
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					*.objdump*
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					*.signature.output
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					examples/asm/sumtest/sumtest
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