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hptw: Simplifed out AnyTLBMiss

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This commit is contained in:
David Harris 2021-07-17 12:07:51 -04:00
parent 784e6cf538
commit ea2aa469a1
1 changed files with 3 additions and 6 deletions
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9
wally-pipelined/src/mmu/pagetablewalker.sv
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@ -92,7 +92,6 @@ module pagetablewalker
logic PRegEn;
logic SelDataTranslation;
logic AnyTLBMissM;
logic [`SVMODE_BITS-1:0] SvMode;
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
@ -111,14 +110,12 @@ module pagetablewalker
flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, CurrentPTE); // Capture page table entry from data cache
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
assign AnyTLBMissM = DTLBMissM | ITLBMissF;
assign StartWalk = (WalkerState == IDLE) & AnyTLBMissM;
assign StartWalk = (WalkerState == IDLE) & (DTLBMissM | ITLBMissF);
assign EndWalk = (WalkerState == LEAF) || (WalkerState == FAULT);
// Assign PTE descriptors common across all XLEN values
assign {Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid} = CurrentPTE[7:0];
assign LeafPTE = Executable | Writable | Readable;
assign LeafPTE = Executable | Readable; // leaf PTE never has only Writable
assign ValidPTE = Valid && ~(Writable && ~Readable);
assign ADPageFault = ~Accessed | (MemWrite & ~Dirty);
@ -209,7 +206,7 @@ module pagetablewalker
// Walker FSM
always_comb
case (WalkerState)
IDLE: if (AnyTLBMissM) NextWalkerState = InitialWalkerState;
IDLE: if (StartWalk) NextWalkerState = InitialWalkerState;
else NextWalkerState = IDLE;
LEVEL3_SET_ADRE: NextWalkerState = LEVEL3_WDV;
LEVEL3_WDV: if (HPTWStall) NextWalkerState = LEVEL3_WDV;